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ds610 october 4, 2010 www.xilinx.com product specification 1 ? copyright 2007?2010 xilinx, inc. xilinx, the xilinx logo, virt ex, spartan, ise, and other designated brands included herein a re trademarks of xilinx in the united states and other countries. pci and pci-x are trademarks of pci-sig and used under license. all other trademarks are the property of their respective owners. module 1: introduction and ordering information ds610 (v3.0) october 4, 2010 ? introduction ? features ? architectural overview ? configuration overview ? general i/o capabilities ? supported packages and package marking ? ordering information module 2: functional description ds610 (v3.0) october 4, 2010 the functionality of the spartan?-3a dsp fpga family is described in the following documents. ? ug331 : spartan-3 generation fpga user guide ? clocking resources ? digital clock managers (dcms) ?block ram ? configurable logic blocks (clbs) - distributed ram - srl16 shift registers - carry and arithmetic logic ? i/o resources ? programmable interconnect ? ise? software design tools and ip cores ? embedded processing and control solutions ? pin types and package overview ? package drawings ? powering fpgas ? power management ? ug332 : spartan-3 generation configuration user guide ? configuration overview ? configuration pins and behavior ? bitstream sizes ? detailed descriptions by mode - master serial mode using platform flash prom - master spi mode using commodity serial flash - master bpi mode using commodity parallel flash - slave parallel (selectmap) using a processor - slave serial using a processor - jtag mode ? ise impact programming examples ? multiboot reconfiguration ? design authentication using device dna ? ug431 : xtremedsp? dsp48a for spartan-3a dsp fpgas user guide ? dsp48a slice design considerations ? dsp48a architecture highlights - 18 x 18-bit multipliers - 48-bit accumulator - 18-bit pre-adder ? dsp48a application examples module 3: dc and switching characteristics ds610 (v3.0) october 4, 2010 ? dc electrical characteristics ? absolute maximum ratings ? supply voltage specifications ? recommended operating conditions ? switching characteristics ? i/o timing ? configurable logic block (clb) timing ? digital clock manager (dcm) timing ? block ram timing ? xtremedsp slice timing ? configuration and jtag timing module 4: pinout descriptions ds610 (v3.0) october 4, 2010 ? pin descriptions ? package overview ? pinout tables ? footprint diagrams 1 spartan-3a dsp fpga family data sheet ds610 october 4, 2010 product specification
ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 2 ? copyright 2007?2010 xilinx, inc. xilinx, the xilinx logo, virt ex, spartan, ise, and other designated brands included herein a re trademarks of xilinx in the united states and other countries. pci and pci-x are trademarks of pci-sig and used under license. all other trademarks are the property of their respective owners. introduction the spartan?-3a dsp family of field-programmable gate arrays (fpgas) solves the design challenges in most high- volume, cost-sensitive, high-performance dsp applications. the two-member family offers densities ranging from 1.8 to 3.4 million system gates, as shown in ta bl e 1 . the spartan-3a dsp family builds on the success of the spartan-3a fpga family by incr easing the amount of memory per logic and adding xtremedsp? dsp48a slices. new features improve system performance and reduce the cost of configuration. these spartan-3a dsp fpga enhancements, combined with proven 90 nm process technology, deliver more functionality and bandwidth per dollar than ever before, setting the new standard in the programmable logic and dsp processing industry. the spartan-3a dsp fpgas exte nd and enhance the spartan-3a fpga family. the xc3sd1800a and the xc3sd3400a devices are tailored for dsp applications and have additional block ram and xtremedsp dsp48a slices. the xtremedsp dsp48a slices replace the 18x18 multipliers found in the spartan-3a devices and are based on the dsp48 blocks found in the virtex?-4 devices. the block rams are also enhanced to run faster by adding an output register. both the block ram and dsp48a slices in the spartan-3a dsp devices run at 250 mhz in the lowest cost, standard -4 speed grade. because of their exceptional dsp price/performance ratio, spartan-3a dsp fpgas are ideally suited to a wide range of consumer electronics applications, such as broadband access, home networking, display/projection, and digital television. the spartan-3a dsp family is a superior alternative to mask programmed asics. fpgas avoid the high initial cost, lengthy development cycles, and the inherent inflexibility of conventional asics. also, fpga programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with asics. features ? very low cost, high-performance dsp solution for high-volume, cost-conscious applications ? 250 mhz xtremedsp dsp48a slices ? dedicated 18-bit by 18-bit multiplier ? available pipeline stages for enhanced performance of at least 250 mhz in the standard -4 speed grade ? 48-bit accumulator for multiply-accumulate (mac) operation ? integrated adder for complex multiply or multiply-add operation ? integrated 18-bit pre-adder ? optional cascaded multiply or mac ? hierarchical selectram? memory architecture ? up to 2268 kbits of fast block ram with byte write enables for processor applications ? up to 373 kbits of efficient distributed ram ? registered outputs on the block ram with operation of at least 280 mhz in the standard -4 speed grade ? dual-range v ccaux supply simplifies 3.3v-only design ? suspend, hibernate mo des reduce system power ? low-power option reduces quiescent current ? multi-voltage, multi-standard selectio? interface pins ? up to 519 i/o pins or 227 differential signal pairs ? lvcmos, lvttl, hstl, and sstl single-ended i/o ? 3.3v, 2.5v, 1.8v, 1.5v, and 1.2v signaling ? selectable output drive, up to 24 ma per pin ? quietio standard reduces i/o switching noise ? full 3.3v 10% compatibility and hot swap compliance ? 622+ mb/s data transfer rate per differential i/o ? lvds, rsds, mini-lvds, hstl/sstl differential i/o with integrated differential termination resistors ? enhanced double data rate (ddr) support ? ddr/ddr2 sdram support up to 333 mb/s ? fully compliant 32-/64-bit, 33/66 mhz pci support ? abundant, flexible logic resources ? densities up to 53712 logic cells, including optional shift register ? efficient wide multiplexers, wide logic, fast carry logic ? ieee 1149.1/1532 jtag programming/debug port ? eight digital clock managers (dcms) ? clock skew elimination (delay locked loop) ? frequency synthesis, multiplication, division ? high-resolution phase shifting ? wide frequency range (5 mhz to over 320 mhz) ? eight low-skew global clock networks, eight additional clocks per half device, plus abundant low-skew routing ? configuration interface to industry-standard proms ? low-cost, space-saving spi serial flash prom ? x8 or x8/x16 bpi parallel nor flash prom ? low-cost xilinx? platform flash with jtag ? unique device dna identifier for design authentication ? load multiple bitstreams under fpga control ? post-configuration crc checking ? microblaze ? and picoblaze ? embedded processor cores ? bga and csp packaging with pb-free options ? common footprints support easy density migration ? xa automotive version available 6 spartan-3a dsp fpga family: introduction and ordering information ds610 (v3.0) october 4, 2010 product specification table 1: summary of spartan-3a dsp fpga attributes device system gates equivalent logic cells clb array (one clb = four slices) distributed ram bits (1) block ram bits (1) dsp48as dcms maximum user i/o maximum differential i/o pairs rows columns total clbs total slices xc3sd1800a 1800k 37,440 88 48 4,160 16,640 260k 1512k 84 8 519 227 xc3sd3400a 3400k 53,712 104 58 5,968 23,872 373k 2268k 126 8 469 213 notes: 1. by convention, one kb is equivalent to 1,024 bits.
spartan-3a dsp fpga family: introduction and ordering information ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 3 architectural overview the spartan-3a dsp family architecture consists of five fundamental programmable functional elements: ? xtremedsp? dsp48a slice provides an 18-bit x 18-bit multiplier, 18-b it pre-adder, 48-bit post-adder/accumulator, an d cascade capabilities for various dsp applications. ? block ram provides data storage in the form of 18-kbit dual-port blocks. ? configurable logic blocks (clbs) contain flexible look-up tables (luts) that implement logic plus storage elements used as flip-flops or latches. clbs perform a wide variety of logical functions as well as store data. ? input/output blocks (iobs) control the flow of data between the i/o pins and the internal logic of the device. iobs support bidirectional data flow plus 3-state operation. supports a variety of signal standards, including several high-performance differential standards. double data-rate (ddr) registers are included. ? digital clock manager (dcm) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals. these elements are organized as shown in figure 1 . a dual ring of staggered iobs surrounds a regular array of clbs. the xc3sd1800a has four columns of dsp48as, and the xc3sd3400a has five columns of dsp48as. each dsp48a has an associated block ram. the dcms are positioned in the center with two at the top and two at the bottom of the device and in the two outer columns of the 4 or 5 columns of block ram and dsp48as. the spartan-3a dsp family features a rich network of routing that interconnect all five functional elements, transmitting signals among them. each functional element has an associated switch matrix that permits multiple connections to the routing. x-ref target - figure 1 figure 1: spartan-3a dsp family architecture clb block ram dcm iobs iobs ds610-1_01_031207 iobs iobs dcm block ram / dsp48a slice dcm clbs iobs dsp48a slice notes: 1. the xc3sd1800a and xc3sd3400a have two dcms on both the left and right sides, as well as the two dcms at the top and bottom of the devices. the two dcms on the left and right of the chips are in the middle of the outer block ram/dsp48a columns of the 4 or 5 columns in the selected device, as shown in the diagram above. 2. a detailed diagram of the dsp48a can be found in ug431 : xtremedsp dsp48a for spart an-3a dsp fpgas user guide.
spartan-3a dsp fpga family: introduction and ordering information ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 4 configuration spartan-3a dsp fpgas are programmed by loading configuration data into robust, reprogrammable, static cmos configuration latches (ccl s) that collectively control all functional elements and routing resources. the fpga?s configuration data is stored ex ternally in a prom or some other non-volatile medium, either on or off the board. after applying power, the configuration data is written to the fpga using any of seven different modes: ? master serial from a xilinx platform flash prom ? serial peripheral interface (spi) from an industry-standard spi serial flash ? byte peripheral interface (bpi) up from an industry-standard x8 or x8/x16 parallel nor flash ? slave serial, typically downloaded from a processor ? slave parallel, typically downloaded from a processor ? boundary scan (jtag), typically downloaded from a processor or system tester furthermore, spartan-3a dsp fpgas support multiboot configuration, allowing two or more fpga configuration bitstreams to be stored in a single spi serial flash or a bpi parallel nor flash. the fpga application controls which configuration to load next and when to load it. additionally, each spartan-3a dsp fpga contains a unique, factory-programmed device dna identifier useful for tracking purposes, anti-cloning designs, or ip protection. i/o capabilities the spartan-3a dsp fpga selectio interface supports many popular single-ended and differential standards. ta b l e 2 shows the number of user i/os as well as the number of differential i/o pairs available for each device/package combination. some of the user i/os are unidirectional input-only pins as indicated in ta b l e 2 . spartan-3a dsp fpgas support the following single-ended standards: ? 3.3v low-voltage ttl (lvttl) ? low-voltage cmos (lvcmos) at 3.3v, 2.5v, 1.8v, 1.5v, or 1.2v ? 3.3v pci at 33 mhz or 66 mhz ? hstl i, ii, and iii at 1.5v and 1.8v, commonly used in memory applications ? sstl i and ii at 1.8v, 2.5v, and 3.3v, commonly used for memory applications ? spartan-3a dsp fpgas support the following differential standards: ? lvds, mini-lvds, rsds, and ppds i/o at 2.5v or 3.3v ? bus lvds i/o at 2.5v ? tmds i/o at 3.3v ? differential hstl and sstl i/o ? lvpecl inputs at 2.5v or 3.3v ta bl e 2 : available user i/os and differential (diff) i/o pairs device cs484 csg484 fg676 fgg676 user diff user diff xc3sd1800a 309 (1) (60) 140 (78) 519 (110) 227 (131) xc3sd3400a 309 (60) 140 (78) 469 (60) 213 (117) notes: 1. the number shown in bold indicates the maximum number of i/o and input-only pins. the number shown in ( italics ) indicates the number of input-only pins. the differential (diff) i nput-only pin count includes bot h differential pairs on i nput-only pins and different ial pairs on i/o pins within i/o banks that are restricted to differential inputs.
spartan-3a dsp fpga family: introduction and ordering information ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 5 package marking figure 2 shows the top marking for spartan-3a dsp fpgas. the ? 5c ? and ? 4i ? speed grade/temperature range part combinations may be dual marked as ? 5c/4i ?. devices with the dual mark can be used as either -5c or -4i devices. devices with a single mark are only guaranteed for the marked speed grade and temperature range. ordering information spartan-3a dsp fpgas are available in both standard and pb-free packaging options for all device/package combinations. the pb-free packages include a ?g? character in the ordering code. x-ref target - figure 2 figure 2: spartan-3a dsp fpga package marking example device speed grade package type / number of pins power/temperature range (t j ) xc3sd1800a -4 standard performance cs484/ csg484 484-ball chip-scale ball grid array (csbga) c commercial (0c to 85c) xc3sd3400a -5 high performance (1) fg676/ fgg676 676-ball fine-pitch ball grid array (f bga) i industrial (?40c to 100c) li low-power industrial (?40c to 100c) (2) notes: 1. the -5 speed grade is exclusively available in the commercial temperature range. 2. the low-power option (li) is exclusively available in the cs(g)484 package and industrial temperature range. 3. see ds705 , xa spartan-3a dsp automotive fpga family data sheet for the xa automotive spartan-3a dsp fpgas. lot code d a te code l4 i spartan device type bga b a ll a1 p a ck a ge low-power (option a l) s peed gr a de oper a ting r a nge r r d s 610-1_02_070607 c s g4 8 4 x gq #### x#######x m as k revi s ion f ab ric a tion/ proce ss code xc 3s d1 8 00a -4 cs 484 li device type speed grade power/temperature range package type number of pins example: ds610-1_05_021009 xc3sd1800a
spartan-3a dsp fpga family: introduction and ordering information ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 6 revision history the following table shows the revision history for this document. notice of disclaimer the xilinx hardware fpga and cpld devices referred to herein (?products?) are subject to the terms and conditions of the xilinx limite d warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of products in an application or environment that is not within the specifications stated in the xilinx data sheet. all specifications are subject to change without notice. products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance, such as life-support or safety devic es or systems, or any other application that invokes the potential risks of death, personal injury, or property or environmental damage (?critical applications?). use of products in critical applications is at the sole risk of customer, subject to applicable laws and regulations. critical applications disclaimer xilinx products (including hardware , software and/or ip cores) ar e not designed or intended to be fail-safe, or for use in any application requirin g fail-safe performance, such as in life-support or safety devices or systems, class iii medical devices, nuclear faciliti es, applications related to the deployment of airbags, or any other applications th at could lead to death, personal injury or severe property or environmental damage (individually an d collectively, ?critical applications?). furthermore, xilinx products are not designed or intended for u se in any applications that affect control of a vehicle or aircraft, unless there is a fail-safe or redundancy feature (which does not include use of software in the xilinx device to implement the re dundancy) and a warning signal upon failure to the operator. customer agrees, prior to using or di stributing any systems that incorporate xilinx products, to thoroughly test the same for saf ety purposes. to the maximum extent permitted by applicable law, customer assumes the sole risk and liabi lity of any use of xili nx products in critical applications. automotive applications disclaimer xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as applicat ions related to: (i) the deployment of airbags, (ii) control of a vehicle, unless there is a fail-safe or redundancy fe ature (which does not incl ude use of software in the xilinx device to implement the redundancy) and a wa rning signal upon failure to the operator, or (iii) uses that could lead to death or personal injury. cu stomer assumes the sole risk and liability of any use of xilinx products in such applications. date version revision 04/02/07 1.0 initial xilinx release. 05/25/07 1.0.1 minor edits. 06/18/07 1.2 updated for production release. 07/16/07 2.0 added low-power options. 06/02/08 2.1 added reference to scd 4103 for 750 mbps performance. add dual mark clarification to package marking . updated links. 03/11/09 2.2 simplified ordering information. removed reference to scd 4103. 10/04/10 3.0 updated the notice of disclaimer section.
ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 7 ? copyright 2007?2010 xilinx, inc. xilinx, the xilinx logo, virt ex, spartan, ise, and other designated brands included herein a re trademarks of xilinx in the united states and other countries. pci and pci-x are trademarks of pci-sig and used under license. all other trademarks are the property of their respective owners. spartan-3a dsp fpga design documentation the functionality of the spartan?-3a dsp fpga family is described in the following documents. the topics covered in each guide are listed. ? ds706 : e xtended spartan-3a family overview ? ug331 : spartan-3 generation fpga user guide ? clocking resources ? digital clock managers (dcms) ? block ram ? configurable logic blocks (clbs) - distributed ram - srl16 shift registers - carry and arithmetic logic ? i/o resources ? programmable interconnect ? ise? software design tools ?ip cores ? embedded processing and control solutions ? pin types and package overview ? package drawings ? powering fpgas ? power management ? ug332 : spartan-3 generation configuration user guide ? configuration overview - configuration pins and behavior - bitstream sizes ? detailed descriptions by mode - master serial mode using xilinx platform flash prom - master spi mode using commodity spi serial flash prom - master bpi mode using commodity parallel nor flash prom - slave parallel (selectmap) using a processor - slave serial using a processor - jtag mode ? ise impact programming examples ? multiboot reconfiguration ? design authentication using device dna ? ug431 : xtremedsp dsp48a for spartan-3a dsp fpgas user guide ? xtremedsp dsp48a slices ? xtremedsp dsp48a pre-adder for specific hardware examples, please see the spartan-3a dsp fpga starter kit board web pages. ? xtremedsp starter platform?spartan-3a dsp 1800a edition http://www.xilinx.com/products/devkits /hw-sd1800a-dsp-sb-uni-g.htm ? xtremedsp starter kit?spartan-3a dsp 1800a edition http://www.xilinx.com/products/devkits /do-sd1800a-dsp-sk-uni-g.htm ? xtremedsp video starter kit?spartan-3a dsp edition http://www.xilinx.com/products/devkits /do-s3adsp-video-sk-uni-g.htm ? embedded development hw/sw kit?spartan-3a dsp s3d1800a microblaze processor edition http://www.xilinx.com/products/devkits /do-sd1800a-edk-dk-uni-g.htm create a xilinx user accoun t and sign up to receive automatic e-mail notification whenever this data sheet or the associated user guides are updated. ? sign up for alerts on xilinx.com https://secure.xilinx.com/we breg/register.do?group=my profile&languageid=1 8 spartan-3a dsp fpga family: functional description ds610 (v3.0) october 4, 2010 product specification
spartan-3a dsp fpga family: functional description ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 8 revision history the following table shows the revision history for this document. notice of disclaimer the xilinx hardware fpga and cpld devices referred to herein (?products?) are subject to the terms and conditions of the xilinx limite d warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of products in an application or environment that is not within the specifications stated in the xilinx data sheet. all specifications are subject to change without notice. products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance, such as life-support or safety devic es or systems, or any other application that invokes the potential risks of death, personal injury, or property or environmental damage (?critical applications?). use of products in critical applications is at the sole risk of customer, subject to applicable laws and regulations. critical applications disclaimer xilinx products (including hardware , software and/or ip cores) ar e not designed or intended to be fail-safe, or for use in any application requirin g fail-safe performance, such as in life-support or safety devices or systems, class iii medical devices, nuclear faciliti es, applications related to the deployment of airbags, or any other applications th at could lead to death, personal injury or severe property or environmental damage (individually an d collectively, ?critical applications?). furthermore, xilinx products are not designed or intended for u se in any applications that affect control of a vehicle or aircraft, unless there is a fail-safe or redundancy feature (which does not include use of software in the xilinx device to implement the re dundancy) and a warning signal upon failure to the operator. customer agrees, prior to using or di stributing any systems that incorporate xilinx products, to thoroughly test the same for saf ety purposes. to the maximum extent permitted by applicable law, customer assumes the sole risk and liabi lity of any use of xili nx products in critical applications. automotive applications disclaimer xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as applicat ions related to: (i) the deployment of airbags, (ii) control of a vehicle, unless there is a fail-safe or redundancy fe ature (which does not incl ude use of software in the xilinx device to implement the redundancy) and a wa rning signal upon failure to the operator, or (iii) uses that could lead to death or personal injury. cu stomer assumes the sole risk and liability of any use of xilinx products in such applications. date version revision 04/02/07 1.0 initial xilinx release. 05/25/07 1.0.1 minor edits. 06/18/07 1.2 updated for production release. 07/16/07 2.0 added low-power options; no changes to this module. 06/02/08 2.1 updated links. 03/11/09 2.2 added link to ds706 on extended spartan-3a family. 10/04/10 3.0 updated link to sign up for alerts and updated notice of disclaimer .
ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 9 ? copyright 2007?2010 xilinx, inc. xilinx, the xilinx logo, virt ex, spartan, ise, and other designated brands included herein a re trademarks of xilinx in the united states and other countries. pci and pci-x are trademarks of pci-sig and used under license. all other trademarks are the property of their respective owners. dc electrical characteristics in this section, specificat ions may be designated as advance, preliminary, or production. these terms are defined as follows: advance: initial estimates are based on simulation, early characterization, and/or extrapolation from the characteristics of other fam ilies. values are subject to change. use as estimates, not for production. preliminary: based on characterization. further changes are not expected. production: these specifications are approved once the silicon has been characterized over numerous production lots. parameter values are considered stable with no future changes expected. all parameter limits are representative of worst-case supply voltage and junction temperature conditions. unless otherwise noted, the published parameter values apply to all spartan ? -3a dsp devices. ac and dc characteristics are specified using the same numbers for both commercial and industrial grades. absolute maximum ratings stresses beyond those listed under ta bl e 3 : absolute maximum ratings may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the recommended operating conditions is not implied. exposure to absolute maximum conditions for extended periods of time adve rsely affects device reliability. 61 spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 product specification ta bl e 3 : absolute maximum ratings symbol description cond itions min max units v ccint internal supply voltage ?0.5 1.32 v v ccaux auxiliary supply voltage ?0.5 3.75 v v cco output driver supply voltage ?0.5 3.75 v v ref input reference voltage ?0.5 v cco +0.5 v v in voltage applied to all user i/o pins and dual-purpose pins driver in a high-impedance state ?0.95 4.6 v voltage applied to all dedicated pins ?0.5 4.6 v i ik input clamp current per i/o pin ?0.5v < v in <(v cco +0.5v) (1) ?100ma v esd electrostatic discharge voltage human body model 2000 v ? charged device model ?500v machine model ?200v t j junction temperature ?125c t stg storage temperature ?65 150 c notes: 1. upper clamp applies only when using pci iostandards. 2. for soldering guidelines, see ug112 : device packaging and thermal characteristics and xapp427 : implementation and solder reflow guidelines for pb-free packages .
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 10 power supply specifications ta bl e 4 : supply voltage thresholds for power-on reset symbol description min max units v ccintt threshold for the v ccint supply 0.4 1.0 v v ccauxt threshold for the v ccaux supply 1.0 2.0 v v cco2t threshold for the v cco bank 2 supply 1.0 2.0 v notes: 1. v ccint , v ccaux , and v cco supplies to the fpga can be applied in any order. howeve r, the fpga configuration source (platform flash, spi flash, parallel nor flash, microcontroller) might have specific requirements. check the data sheet for the attached configurati on source. apply v ccint last for lowest overall power consumption (see the ug331 chapter titled "powering spartan-3 generation fpgas" for more information). 2. to ensure successful power-on, v ccint , v cco bank 2, and v ccaux supplies must rise through their respective threshold-voltage ranges with no dips at any point. ta bl e 5 : supply voltage ramp rate symbol description min max units v ccintr ramp rate from gnd to valid v ccint supply level 0.2 100 ms v ccauxr ramp rate from gnd to valid v ccaux supply level 0.2 100 ms v cco2r ramp rate from gnd to valid v cco bank 2 supply level 0.2 100 ms notes: 1. v ccint , v ccaux , and v cco supplies to the fpga can be applied in any order. howeve r, the fpga configuration source (platform flash, spi flash, parallel nor flash, microcontroller) might have specific requirements. check the data sheet for the attached configurati on source. apply v ccint last for lowest overall power consumption (see the ug331 chapter titled "powering spartan-3 generation fpgas" for more information). 2. to ensure successful power-on, v ccint , v cco bank 2, and v ccaux supplies must rise through their respective threshold-voltage ranges with no dips at any point. ta bl e 6 : supply voltage levels necessary for preserving cmos configuration latch (ccl) contents and ram data symbol description min units v drint v ccint level required to retain cmos configuration latch (ccl) and ram data 1.0 v v draux v ccaux level required to retain cmos configuration latch (ccl) and ram data 2.0 v
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 11 general recommended op erating conditions ta bl e 7 : general recommended operating conditions symbol description min nominal max units t j junction temperature commercial 0 ?85 c industrial ?40 ?100 c v ccint internal supply voltage 1.14 1.20 1.26 v v cco (1) output driver supply voltage 1.10 ?3.60v v ccaux auxiliary supply voltage (2) v ccaux = 2.5 2.25 2.50 2.75 v v ccaux = 3.3 3.00 3.30 3.60 v v in (3) input voltage pci? iostandard ?0.5 ?v cco +0.5 v all other iostandards ip or io_# ?0.5 ?4.10v io_lxxy_# (4) ?0.5 ?4.10v t in input signal transition time (5) ? ? 500 ns notes: 1. this v cco range spans the lowest and highest operating voltages for all supported i/o standards. ta bl e 1 0 lists the recommended v cco range specific to each of the single-ended i/o standards, and ta b l e 1 2 lists that specific to the differential standards. 2. define v ccaux selection using config vccaux constraint. 3. see xapp459 , eliminating i/o coupling effects when interfacing large-swi ng single-ended signals to user i/o pins on spartan-3 families . 4. for single-ended signals that are placed on a differential-capable i/o, v in of ?0.2v to ?0.5v is supported but can cause increased leakage between the two pins. see parasitic leakage in ug331 , spartan-3 generation fpga user guide . 5. measured between 10% and 90% v cco . follow signal integrity recommendations.
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 12 general dc characteristics for i/o pins ta bl e 8 : general dc characteristics of user i/o, dual-purpose, and dedicated pins (1) symbol description test conditions min typ max units i l (2) leakage current at user i/o, input-only, dual-purpose, and dedicated pins, fpga powered driver is in a high-impedance state, v in =0v or v cco max, sample-tested ?10 ?+10a i hs leakage current on pins during hot socketing, fpga unpowered all pins except init_b, prog_b, done, and jtag pins when pudc_b = 1. ?10 ?+10a init_b, prog_b, done, and jtag pins or other pins when pudc_b = 0. add i hs + i rpu a i rpu (3) current through pull-up resistor at user i/o, dual-purpose, input-only, and dedicated pins. dedicated pins are powered by v ccaux . v in = gnd v cco or v ccaux = 3.0v to 3.6v ?151 ?315 ?710 a v cco or v ccaux = 2.3v to 2.7v ?82 ?182 ?437 a v cco = 1.7v to 1.9v ?36 ?88 ?226 a v cco = 1.4v to 1.6v ?22 ?56 ?148 a v cco = 1.14v to 1.26v ?11 ?31 ?83 a r pu (3) equivalent pull-up resistor value at user i/o, dual-purpose, input-only, and dedicated pins (based on i rpu per note 2) v in = gnd v cco = 3.0v to 3.6v 5.1 11.4 23.9 k v cco = 2.3v to 2.7v 6.2 14.8 33.1 k v cco = 1.7v to 1.9v 8.4 21.6 52.6 k v cco = 1.4v to 1.6v 10.8 28.4 74.0 k v cco = 1.14v to 1.26v 15.3 41.1 119.4 k i rpd (3) current through pull-down resistor at user i/o, dual-purpose, input-only, and dedicated pins v in = v cco v ccaux = 3.0v to 3.6v 167 346 659 a v ccaux = 2.25v to 2.75v 100 225 457 a r pd (3) equivalent pull-down resistor value at user i/o, dual-purpose, input-only, and dedicated pins (based on i rpd per note 2) v ccaux = 3.0v to 3.6v v in = 3.0v to 3.6v 5.5 10.4 20.8 k v in = 2.3v to 2.7v 4.1 7.8 15.7 k v in = 1.7v to 1.9v 3.0 5.7 11.1 k v in = 1.4v to 1.6v 2.7 5.1 9.6 k v in = 1.14v to 1.26v 2.4 4.5 8.1 k v ccaux = 2.25v to 2.75v v in = 3.0v to 3.6v 7.9 16.0 35.0 k v in = 2.3v to 2.7v 5.9 12.0 26.3 k v in = 1.7v to 1.9v 4.2 8.5 18.6 k v in = 1.4v to 1.6v 3.6 7.2 15.7 k v in = 1.14v to 1.26v 3.0 6.0 12.5 k i ref v ref current per pin all v cco levels ?10 ?+10a c in input capacitance ? ? ?10pf r dt resistance of optional differential termination circuit within a differential i/o pair. not available on input-only pairs. v cco = 3.3v 10% lvds_33, mini_lvds_33, rsds_33 90 100 115 v cco = 2.5v 10% lvds_25, mini_lvds_25, rsds_25 90 110 ? notes: 1. the numbers in this table are based on the conditions set forth in ta bl e 7 . 2. for single-ended signals that are placed on a differential-capable i/o, v in of ?0.2v to ?0.5v is supported but can cause increased leakage between the two pins. see parasitic leakage in ug331 , spartan-3 generation fpga user guide . 3. this parameter is based on characterization. the pull-up resistance r pu = v cco /i rpu . the pull-down resistance r pd =v in /i rpd .
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 13 quiescent current requirements ta bl e 9 : quiescent supply current characteristics (1) symbol description device power typical (2) commercial maximum (2) industrial maximum (2) units i ccintq quiescent v ccint supply current xc3sd1800a c,i 41 390 500 ma li 36 ? 175 ma xc3sd3400a c,i 64 550 725 ma li 55 ? 300 ma i ccoq quiescent v cco supply current xc3sd1800a c,i 0.4 4 5 ma li 0.2 ?5ma xc3sd3400a c,i 0.4 4 5 ma li 0.2 ?5ma i ccauxq quiescent v ccaux supply current xc3sd1800a c,i 25 90 110 ma li 24 ?72ma xc3sd3400a c,i 39 130 160 ma li 38 ? 105 ma notes: 1. the numbers in this table are based on the conditions set forth in ta bl e 7 . 2. quiescent supply current is measured with all i/o drivers in a high-impedance state and with all pull-up/pull-down resistors at the i/o pads disabled. typical values are characterized using typical devices at room temperature (t j of 25c at v ccint = 1.2v, v cco = 3.3v, and v ccaux = 2.5v). the maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage limits with v ccint = 1.26v, v cco = 3.6v, and v ccaux = 3.6v. the fpga is programmed with a ?blank? configuration data file (that is, a design with no functional elements instantiated). for conditions other than those described above (for example, a design including fun ctional elements), measured quiescent current levels will be different than the values in the table. 3. for more accurate estimates for a specific design, use the xilinx xpower tools. there are two recommended ways to estimate th e total power consumption (quiescent plus dynamic) for a specific design: a) the spartan-3a dsp fpga xpower estimator provides quick, approximate, typical estimates, and does not require a netlist of the design. b) xpower analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates. 4. the maximum numbers in this table indicate the minimum current each power rail requires in order for the fpga to power-on suc cessfully. 5. for information on the power-saving suspend mode, see xapp480 : using suspend mode in spartan-3 generation fpgas . suspend mode typically saves 40% total power consumption compared to quiescent current.
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 14 single-ended i/o standards ta bl e 1 0 : recommended operating conditions for u ser i/os using single-ended standards iostandard attribute v cco for drivers (2) v ref v il v ih (3) min (v) nom (v) max (v) min (v) nom (v) max (v) max (v) min (v) lv t t l 3 . 0 3 . 3 3 . 6 v ref is not used for these i/o standards 0.8 2.0 lv c m o s 3 3 (4) 3.0 3.3 3.6 0.8 2.0 lv c m o s 2 5 (4,5) 2.3 2.5 2.7 0.7 1.7 lvcmos18 1.65 1.8 1.95 0.4 0.8 lvcmos15 1.4 1.5 1.6 0.4 0.8 lvcmos12 1.1 1.2 1.3 0.4 0.7 pci33_3 (6) 3.0 3.3 3.6 0.3 ? v cco 0.5 ? v cco pci66_3 (6) 3.0 3.3 3.6 0.3 ? v cco 0.5 ? v cco hstl_i 1.4 1.5 1.6 0.68 0.75 0.9 v ref ?0.1 v ref +0.1 hstl_iii 1.4 1.5 1.6 ?0.9 ?v ref ?0.1 v ref +0.1 hstl_i_18 1.7 1.8 1.9 0.8 0.9 1.1 v ref ?0.1 v ref +0.1 hstl_ii_18 1.7 1.8 1.9 ?0.9 ?v ref ?0.1 v ref +0.1 hstl_iii_18 1.7 1.8 1.9 ?1.1 ?v ref ?0.1 v ref +0.1 sstl18_i 1.7 1.8 1.9 0.833 0.900 0.969 v ref ?0.125 v ref +0.125 sstl18_ii 1.7 1.8 1.9 0.833 0.900 0.969 v ref ?0.125 v ref +0.125 sstl2_i 2.3 2.5 2.7 1.13 1.25 1.38 v ref ?0.150 v ref +0.150 sstl2_ii 2.3 2.5 2.7 1.13 1.25 1.38 v ref ?0.150 v ref +0.150 sstl3_i 3.0 3.3 3.6 1.3 1.5 1.7 v ref ?0.2 v ref +0.2 sstl3_ii 3.0 3.3 3.6 1.3 1.5 1.7 v ref ?0.2 v ref +0.2 notes: 1. descriptions of the symbols used in this table are as follows: v cco ?the supply voltage for output drivers v ref ?the reference voltage for setting the input switching threshold v il ?the input voltage that indicates a low logic level v ih ?the input voltage that indicates a high logic level 2. in general, the v cco rails supply only output drivers, not input circuits. the exceptions are for lvcmos25 inputs when v ccaux = 3.3v range and for pci i/o standards. 3. for device operation, the maximum signal voltage (v ih max) can be as high as v in max. see ta b l e 7 . 4. there is approximately 100 mv of hysteresis on inputs using lvcmos33 and lvcmos25 i/o standards. 5. all dedicated pins (prog_b, done, suspend, tc k, tdi, tdo, and tms) draw power from the v ccaux rail and use the lvcmos25 or lvcmos33 standard depending on v ccaux . the dual-purpose configuration pins use t he lvcmos standard before the user mode. when using these pins as part of a standard 2.5v configuration interface, apply 2.5v to the v cco lines of banks 0, 1, and 2 at power-on as well as throughout configuration. 6. for information on pci ip solutions, see www.xilinx.com/pci . the pci iostandard is not supported on input-only pins. the pcix iostandard is available and has equivalent characteristics but no pci-x ip is supported.
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 15 ta bl e 1 1 : dc characteristics of user i/os using single-ended standards iostandard attribute test conditions logic level characteristics i ol (ma) i oh (ma) v ol max (v) v oh min (v) lv t t l (3) 2 2 ?2 0.4 2.4 44?4 66?6 88?8 12 12 ?12 16 16 ?16 24 24 ?24 lv c m o s 3 3 (3) 2 2 ?2 0.4 v cco ? 0.4 44?4 66?6 88?8 12 12 ?12 16 16 ?16 24 (5) 24 ?24 lv c m o s 2 5 (3) 2 2 ?2 0.4 v cco ? 0.4 44?4 66?6 88?8 12 12 ?12 16 (5) 16 ?16 24 (5) 24 ?24 lv c m o s 1 8 (3) 2 2 ?2 0.4 v cco ? 0.4 44?4 66?6 88?8 12 (5) 12 ?12 16 (5) 16 ?16 lv c m o s 1 5 (3) 2 2 ?2 0.4 v cco ? 0.4 44?4 66?6 8 (5) 8?8 12 (5) 12 ?12 lv c m o s 1 2 (3) 2 2 ?2 0.4 v cco ? 0.4 4 (5) 4?4 6 (5) 6?6 pci33_3 (4) 1.5 ?0.5 10% v cco 90% v cco pci66_3 (4) 1.5 ?0.5 10% v cco 90% v cco hstl_i (5) 8?8 0.4 v cco ? 0.4 hstl_iii (5) 24 ?8 0.4 v cco ? 0.4 hstl_i_18 8 ?8 0.4 v cco ? 0.4 hstl_ii_18 (5) 16 ?16 0.4 v cco ? 0.4 hstl_iii_18 24 ?8 0.4 v cco ? 0.4 sstl18_i 6.7 ?6.7 v tt ? 0.475 v tt + 0.475 sstl18_ii (5) 13.4 ?13.4 v tt ? 0.603 v tt + 0.603 sstl2_i 8.1 ?8.1 v tt ? 0.61 v tt +0.61 sstl2_ii (5) 16.2 ?16.2 v tt ? 0.81 v tt +0.81 sstl3_i 8 ?8 v tt ? 0.6 v tt +0.6 sstl3_ii (5) 16 ?16 v tt ? 0.8 v tt +0.8 notes: 1. the numbers in this table are based on the conditions set forth in ta bl e 7 and ta b l e 1 0 . 2. descriptions of the symbols used in this table are as follows: i ol ?the output current condition under which vol is tested i oh ?the output current condition under which voh is tested v ol ? the output voltage that indicates a low logic level v oh ?the output voltage that indicates a high logic level v cco ?the supply voltage for output drivers v tt ?the voltage applied to a resistor termination 3. for the lvcmos and lvttl standards: the same v ol and v oh limits apply for the fast, slow, and quietio slew attributes. 4. tested according to the relevant pci specifications. for information on pci ip solutions, see www.xilinx.com/products/ design_resources/conn_central/protocols/pci_pcix.htm . the pcix iostandard is available and has equivalent characteristics but no pci-x ip is supported. 5. these higher-drive output standards are supported only on fpga banks 1 and 3. inputs are unrestricted. see the using i/o resources chapter in ug331 . ta b l e 1 1 : dc characteristics of user i/os using single-ended standards (cont?d) iostandard attribute test conditions logic level characteristics i ol (ma) i oh (ma) v ol max (v) v oh min (v)
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 16 differential i/o standards differential input pairs x-ref target - figure 3 figure 3: differential input voltages ta bl e 1 2 : recommended operating conditions for user i/os using differential signal standards iostandard attribute v cco for drivers (1) v id v icm (2) min (v) nom (v) max (v) min (mv) nom (mv) max (mv) min (v) nom (v) max (v) lv d s _ 2 5 (3) 2.25 2.5 2.75 100 350 600 0.3 1.25 2.35 lv d s _ 3 3 (3) 3.0 3.3 3.6 100 350 600 0.3 1.25 2.35 blvds_25 (4) 2.25 2.5 2.75 100 300 ?0.31.32.35 mini_lvds_25 (3) 2.25 2.5 2.75 200 ? 600 0.3 1.2 1.95 mini_lvds_33 (3) 3.0 3.3 3.6 200 ? 600 0.3 1.2 1.95 lvpecl_25 (5) inputs only 100 800 1000 0.3 1.2 1.95 lvpecl_33 (5) inputs only 100 800 1000 0.3 1.2 2.8 (6) rsds_25 (3) 2.25 2.5 2.75 100 200 ?0.31.21.5 rsds_33 (3) 3.0 3.3 3.6 100 200 ?0.31.21.5 tmds_33 ( 3 , 4 , 7 ) 3.14 3.3 3.47 150 ? 1200 2.7 ?3.23 ppds_25 (3) 2.25 2.5 2.75 100 ? 400 0.2 ?2.3 ppds_33 (3) 3.0 3.3 3.6 100 ? 400 0.2 ?2.3 diff_hstl_i_18 1.7 1.8 1.9 100 ? ?0.8 ?1.1 diff_hstl_ii_18 (8) 1.7 1.8 1.9 100 ? ?0.8 ?1.1 diff_hstl_iii_18 1.7 1.8 1.9 100 ? ?0.8 ?1.1 diff_hstl_i 1.4 1.5 1.6 100 ? ?0.68 ?0.9 diff_hstl_iii 1.4 1.5 1.6 100 ? ? ?0.9 ? diff_sstl18_i 1.7 1.8 1.9 100 ? ?0.7 ?1.1 diff_sstl18_ii (8) 1.7 1.8 1.9 100 ? ?0.7 ?1.1 diff_sstl2_i 2.3 2.5 2.7 100 ? ?1.0 ?1.5 diff_sstl2_ii (8) 2.3 2.5 2.7 100 ? ?1.0 ?1.5 diff_sstl3_i 3.0 3.3 3.6 100 ? ?1.1 ?1.9 diff_sstl3_ii 3.0 3.3 3.6 100 ? ?1.1 ?1.9 notes: 1. the v cco rails supply only differential output drivers, not input circuits. 2. v icm must be less than v ccaux . 3. these true differential output standards are supported only on fpga banks 0 and 2. inputs are unrestricted. see the chapter " using i/o resources" in ug331 . 4. see "external termination requirements for differential i/o." 5. lvpecl is supported on inputs only, not outputs. lvpecl_33 requires v ccaux =3.3v 10%. 6. lvpecl_33 maximum v icm = the lower of 2.8v or v ccaux ?(v id /2). 7. requires v ccaux =3.3v10%. (v ccaux -300 mv) v icm (v ccaux - 37 mv). 8. these higher-drive output standards are supported only on fpga banks 1 and 3. inputs are unrestricted. see the chapter "using i/o resources" in ug331 . 9. all standards except for lvpecl and tmds can have vccaux at either 2.5v or 3.3v. define your vccaux level using the config vc caux constraint. ds610-3_03_061507 v inn v inn v inp v inp gnd level 50% v icm v icm = input common mode voltage = v id internal logic differential i/o pair pins n p 2 v inp + v inn v id = differential input voltage = v inp - v inn
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 17 differential output pairs x-ref target - figure 4 figure 4: differential output voltages ta bl e 1 3 : dc characteristics of user i/os using differential signal standards iostandard attribute v od v ocm v oh v ol min (mv) typ (mv) max (mv) min (v) t yp (v) max (v) min (v) max (v) lvds_25 247 350 454 1.125 ?1.375 ? ? lvds_33 247 350 454 1.125 ?1.375 ? ? blvds_25 240 350 460 ?1.30 ? ? ? mini_lvds_25 300 ? 600 1.0 ?1.4 ? ? mini_lvds_33 300 ? 600 1.0 ?1.4 ? ? rsds_25 100 ? 400 1.0 ?1.4 ? ? rsds_33 100 ? 400 1.0 ?1.4 ? ? tmds_33 400 ?800v cco ? 0.405 ?v cco ? 0.190 ? ? ppds_25 100 ? 400 0.5 0.8 1.4 ? ? ppds_33 100 ? 400 0.5 0.8 1.4 ? ? diff_hstl_i_18 ? ? ? ? ? ?v cco ? 0.4 0.4 diff_hstl_ii_18 ? ? ? ? ? ?v cco ? 0.4 0.4 diff_hstl_iii_18 ? ? ? ? ? ?v cco ? 0.4 0.4 diff_hstl_i ? ? ? ? ? ?v cco ? 0.4 0.4 diff_hstl_iii ? ? ? ? ? ?v cco ? 0.4 0.4 diff_sstl18_i ? ? ? ? ? ?v tt + 0.475 v tt ? 0.475 diff_sstl18_ii ? ? ? ? ? ?v tt + 0.603 v tt ? 0.603 diff_sstl2_i ? ? ? ? ? ?v tt + 0.61 v tt ? 0.61 diff_sstl2_ii ? ? ? ? ? ?v tt + 0.81 v tt ? 0.81 diff_sstl3_i ? ? ? ? ? ? v tt + 0.6 v tt - 0.6 diff_sstl3_ii ? ? ? ? ? ? v tt + 0.8 v tt - 0.8 notes: 1. the numbers in this table are based on the conditions set forth in ta bl e 7 and ta bl e 1 2 . 2. see "external termination requirements for differential i/o." 3. output voltage measurements for all differential standards are made with a termination resistor (r t ) of 100 across the n and p pins of the differential signal pair. 4. at any given time, no more than two of the following differential output standards can be assigned to an i/o bank: lvds_25, r sds_25, mini_lvds_25, ppds_25 when v cco =2.5v, or lvds_33, rsds_33, mini_lvds_33, tmds_33, ppds_33 when v cco =3.3v v outn v outp gnd level 50% v ocm v ocm v od v ol v oh v outp internal logic v outn n p = output common mode voltage = 2 v outp +v outn v od = output differential voltage = v oh = output voltage indicating a high logic level v ol = output voltage indicating a low logic level v outp -v outn differential i/o pair pins d s3 12- 3 _0 3 _090510
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 18 external termination requirements for differential i/o lvds, rsds, mini_lvds, and ppds i/o standards blvds_25 i/o standard tmds_33 i/o standard device dna read endurance x-ref target - figure 5 figure 5: external input termination for lvds, rs ds, mini_lvds, and ppds i/o standards x-ref target - figure 6 figure 6: external output and input termination resistors for blvds_25 i/o standard x-ref target - figure 7 figure 7: external input resistors required for tmds_33 i/o standard ta bl e 1 4 : device dna identifier memory characteristics symbol description minimum units dna_cycles number of read operations or jtag isc_dna read operations. unaffected by hold or shift operations. 30,000,000 read cycles z 0 = 50 z 0 = 50 100 d s 529- 3 _09_020107 a) input-only differential pair s or pair s not u s in g diff_term=ye s con s traint z 0 = 50 z 0 = 50 b) differential pair s u s in g diff_term=ye s con s traint diff_term=no diff_term=yes lv d s _ 33 , mini_lvd s _ 33 , r s d s _ 33 , ppd s _ 33 lv d s _ 33 , lvd s _25, mini_lvd s _ 33 , mini_lvd s _25, r s d s _ 33 , r s d s _25, ppd s _ 33 , ppd s _25 cat16-pt4f4 p a rt n u m b er / th of bo u rn s 1 4 v cco = 3 . 3 v lv d s _25, mini_lvd s _25, r s d s _25, ppd s _25 v cco = 2.5v lv d s _ 33 , mini_lvd s _ 33 , r s d s _ 33 , ppd s _ 33 v cco = 3 . 3 v lv d s _25, mini_lvd s _25, r s d s _25, ppd s _25 v cco = 2.5v no v cco re s triction s r lv d s _ 33 , mini_lvd s _ 33 , r s d s _ 33 , ppd s _ 33 v cco = 3 . 3 v lv d s _25, mini_lvd s _25, r s d s _25, ppd s _25 v cco = 2.5v dt b a nk 0 b a nk 2 b a nk 0 b a nk 2 b a nk 3 b a nk 1 b a nk 0 a nd 2 any b a nk z 0 = 50 z 0 = 50 140 165 165 100 v cco = 2.5v no v cco re qu irement d s 529- 3 _07_020107 blvd s _25 blvd s _25 cat16-lv4f12 p a rt n u m b er / th of bo u rn s 1 4 cat16-pt4f4 p a rt n u m b er / th of bo u rn s 1 4 b a nk 0 b a nk 2 b a nk 3 b a nk 1 any b a nk b a nk 0 b a nk 2 b a nk 3 b a nk 1 any b a nk 50 v cco = 3 . 3 v v ccaux = 3 . 3 v d s 529- 3 _0 8 _020107 dvi/hdmi c ab le 50 3 . 3 v tmd s _ 33 tmd s _ 33 b a nk 0 b a nk 2 b a nk 0 a nd 2 b a nk 0 b a nk 2 b a nk 3 b a nk 1 any b a nk
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 19 switching characteristics all spartan-3a dsp fpgas ship in two speed grades: ?4 and the higher performance ?5. switching characteristics in this document are designated as advance, preliminary, or production, as shown in ta b l e 1 5 . each category is defined as follows: advance : these specifications are based on simulations only and are typically available soon after establishing fpga specifications. although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. preliminary : these specifications are based on complete early silicon characterization . devices and speed grades with this designation are intended to give a better indication of the expected performanc e of production silicon. the probability of under-r eporting preliminary delays is greatly reduced compared to advance data. production : these specifications are approved once enough production s ilicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal notification of any subsequent changes. typically, the slowest speed grades transition to production before faster speed grades. software version requirements production-quality systems must use fpga designs compiled using a speed file designated as production status. fpgas designs using a less mature speed file designation should only be used during system prototyping or pre-production qualification. fpga designs with speed files designated as preview, advance, or preliminary should not be used in a production-quality system. whenever a speed file designation changes, as a device matures toward production stat us, rerun the latest xilinx? ise? software on the fpga design to ensure that the fpga design incorporates the latest timing information and software updates. production designs will require updating the xilinx ise development software with a future version and/or service pack. all parameter limits are representative of worst-case supply voltage and junction temperature conditions. unless otherwise noted, the published parameter values apply to all spartan-3a dsp devices. ac and dc characteristics are specified using the same numbers for both commercial and industrial grades. create a xilinx user accoun t and sign up to receive automatic e-mail notification whenever this data sheet or the associated user guides are updated. ? sign up for alerts on xilinx.com http://www.xilinx.com/supp ort/answers/18683.htm timing parameters and their representative values are selected for inclusion below either because they are important as general design requirements or they indicate fundamental device performance characteristics. the spartan-3a dsp fpga speed files (v1.32), part of the xilinx development software, ar e the original source for many but not all of the values. the speed grade designations for these files are shown in ta bl e 1 5 . for more complete, more precise, and worst-case data, use the values reported by the xilinx st atic timing analyzer (trace in the xilinx development softw are) and back-annotated to the simulation netlist. ta b l e 1 6 provides the recent history of the spartan-3a dsp fpga speed files. ta b l e 1 5 : spartan-3a dsp v1.32 speed grade designations device advance preliminary production xc3sd1800a -4, -5 xc3sd3400a -4, -5 ta b l e 1 6 : spartan-3a dsp speed file version history version ise release description 1.32 ise 10.1.02 updated dsp timing model to reflect higher performance for some implementations 1.31 ise 10.1 added automotive support 1.30 ise 9.2.03i added absolute minimum values 1.29 ise 9.2.01i production speed files for -4 and -5 speed grades 1.28 ise 9.2i minor updates 1.27 ise 9.1.03i advance speed files for -4 speed grade
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 20 i/o timing pin-to-pin clock-to-output times ta bl e 1 7 : pin-to-pin clock-to-output times for the iob output path symbol description conditions device speed grade units -5 -4 max max clock-to-output times t ickofdcm when reading from the output flip-flop (off), the time from the active transition on the global clock pin to data appearing at the output pin. the dcm is in use. lv c m o s 2 5 (2) , 12 ma output drive, fast slew rate, with dcm (3) xc3sd1800a 3.28 3.51 ns xc3sd3400a 3.36 3.82 ns t ickof when reading from off, the time from the active transition on the global clock pin to data appearing at the output pin. the dcm is not in use. lv c m o s 2 5 (2) , 12 ma output drive, fast slew rate, without dcm xc3sd1800a 5.23 5.58 ns xc3sd3400a 5.51 6.13 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 2 6 and are based on the operating conditions set forth in ta b l e 7 and ta bl e 1 0 . 2. this clock-to-output time requires adjustment whenever a signal standard other than lvcmos25 is assigned to the global clock input or a standard other than lvcmos25 with 12 ma drive and fast slew rate is assigned to the data output. if the former is true, add the appropriate input adjustment from ta bl e 2 2 . if the latter is true, add the appropriate output adjustment from ta bl e 2 5 . 3. dcm output jitter is included in all measurements.
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 21 pin-to-pin setup and hold times ta bl e 1 8 : pin-to-pin setup and hold times for the iob input path (system synchronous) symbol description conditions device speed grade units -5 -4 max max setup times t psdcm when writing to the input flip-flop (iff), the time from the setup of data at the input pin to the active transition at a global clock pin. the dcm is in use. no input delay is programmed. lv c m o s 2 5 (2) , ifd_delay_value = 0, with dcm (4) xc3sd1800a 2.65 3.11 ns xc3sd3400a 2.25 2.49 ns t psfd when writing to iff, the time from the setup of data at the input pin to an active transition at the global clock pin. the dcm is not in use. the input delay is programmed. lv c m o s 2 5 (2) , ifd_delay_value = 6, without dcm xc3sd1800a 2.98 3.39 ns xc3sd3400a 2.78 3.08 ns hold times t phdcm when writing to iff, the time from the active transition at the global clock pin to the point when data must be held at the input pin. the dcm is in use. no input delay is programmed. lv c m o s 2 5 (3) , ifd_delay_value = 0, with dcm (4) xc3sd1800a ?0.38 ?0.38 ns xc3sd3400a ?0.26 ?0.26 ns t phfd when writing to iff, the time from the active transition at the global clock pin to the point when data must be held at the input pin. the dcm is not in use. the input delay is programmed. lv c m o s 2 5 (3) , ifd_delay_value = 6, without dcm xc3sd1800a ?0.71 ?0.71 ns xc3sd3400a ?0.65 ?0.65 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 2 6 and are based on the operating conditions set forth in ta b l e 7 and ta bl e 1 0 . 2. this setup time requires adjustment whenever a signal standard other than lvcmos25 is assigned to the global clock input or t he data input. if this is true of the global clock input, subtract the appropriate adjustment from ta b l e 2 2 . if this is true of the data input, add the appropriate input adjustment from the same table. 3. this hold time requires adjustment whenever a signal standard other than lvcmos25 is assigned to the global clock input or th e data input. if this is true of the global clock input, add the appropriate input adjustment from ta bl e 2 2 . if this is true of the data input, subtract the appropriate input adjustment from the same table. when the hold time is negative, it is possible to change the data before the clock?s active edge. 4. dcm output jitter is included in all measurements.
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 22 input setup and hold times ta bl e 1 9 : setup and hold times for the iob input path symbol description conditions delay_ value device speed units -5 -4 min min setup times t iopick time from the setup of data at the input pin to the active transition at the iclk input of the input flip -flop (iff). no input delay is programmed. lv c m o s 2 5 (2) ifd_delay_value=0 xc3sd1800a 1.65 1.81 ns xc3sd3400a 1.51 1.88 ns t iopickd time from the setup of data at the input pin to the active transition at the iclk input of the input f lip-flop (iff). the input delay is programmed. lv c m o s 2 5 (2) 1 xc3sd1800a 2.09 2.24 ns 2 2.67 2.83 ns 3 3.25 3.64 ns 4 3.75 4.20 ns 5 3.69 4.16 ns 6 4.47 5.09 ns 7 5.27 6.02 ns 8 5.79 6.63 ns 1 xc3sd3400a 2.07 2.44 ns 2 2.57 3.02 ns 3 3.44 3.81 ns 4 4.01 4.39 ns 5 3.89 4.26 ns 6 4.43 5.08 ns 7 5.20 5.95 ns 8 5.70 6.55 ns hold times t ioickp time from the active transition at the iclk input of the inpu t flip-flop (iff) to the point where data must be held at the input pin. no input delay is programmed. lv c m o s 2 5 (3) 0 xc3sd1800a ?0.63 ?0.52 ns xc3sd3400a ?0.56 ?0.56 ns
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 23 t ioickpd time from the active transition at the iclk input of the inpu t flip-flop (iff) to the point where data must be held at the input pin. the input delay is programmed. lv c m o s 2 5 (3) 1 xc3sd1800a ?1.40 ?1.40 ns 2 ?2.11 ?2.11 ns 3 ?2.48 ?2.48 ns 4 ?2.77 ?2.77 ns 5 ?2.62 ?2.62 ns 6 ?3.06 ?3.06 ns 7 ?3.42 ?3.42 ns 8 ?3.65 ?3.65 ns 1 xc3sd3400a ?1.31 ?1.31 ns 2 ?1.88 ?1.88 ns 3 ?2.44 ?2.44 ns 4 ?2.89 ?2.89 ns 5 ?2.83 ?2.83 ns 6 ?3.33 ?3.33 ns 7 ?3.63 ?3.63 ns 8 ?3.96 ?3.96 ns set/reset pulse width t rpw_iob minimum pulse width to sr control input on iob ? ? all 1.33 1.61 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 2 6 and are based on the operating conditions set forth in ta b l e 7 and ta bl e 1 0 . 2. this setup time requires adjustment whenever a signal standard other than lvcmos25 is assigned to the data input. if this is true, add the appropriate input adjustment from ta bl e 2 2 . 3. these hold times require adjustment whenever a signal standard ot her than lvcmos25 is assigned to the data input. if this is true, subtract the appropriate input adjustment from ta bl e 2 2 . when the hold time is negative, it is possible to change the data before the clock?s active edge. ta bl e 2 0 : sample window (source synchronous) symbol description max units t samp setup and hold capture window of an iob flip-flop. the input capture sample window value is highly specific to a particular application, device, package, i/o standard, i/o placement, dcm usag e, and clock buffer. please consult the appropriate xilinx answer record for application-specific values. ? answer record 30879 ps ta bl e 1 9 : setup and hold times for the iob input path (cont?d) symbol description conditions delay_ value device speed units -5 -4 min min
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 24 input propagation times ta bl e 2 1 : propagation times for the iob input path symbol description conditions delay_value device speed grade units -5 -4 max max propagation times t iopi the time it takes for data to travel from the input pin to the i output with no input delay programmed lv c m o s 2 5 (2) ibuf_delay_value=0 xc3sd1800a 0.51 0.53 ns xc3sd3400a 0.73 0.93 ns t iopid the time it takes for data to travel from the input pin to the i output with the input delay programmed lv c m o s 2 5 (2) 1 xc3sd1800a 1.29 1.62 ns 2 1.67 2.08 ns 3 1.92 2.36 ns 4 2.38 2.89 ns 5 2.61 3.17 ns 6 2.98 3.55 ns 7 3.30 3.92 ns 8 3.63 4.37 ns 9 3.31 4.02 ns 10 3.69 4.47 ns 11 3.94 4.77 ns 12 4.41 5.27 ns 13 4.67 5.56 ns 14 5.03 5.94 ns 15 5.36 6.31 ns 16 5.64 6.73 ns 1 xc3sd3400a 1.56 1.99 ns 2 1.92 2.44 ns 3 2.18 2.72 ns 4 2.66 3.19 ns 5 2.91 3.43 ns 6 3.27 3.81 ns 7 3.59 4.17 ns 8 3.87 4.58 ns 9 3.52 4.22 ns 10 3.87 4.65 ns 11 4.14 4.94 ns 12 4.68 5.40 ns 13 4.93 5.66 ns 14 5.29 6.06 ns 15 5.61 6.43 ns 16 5.88 6.80 ns
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 25 t iopli the time it takes for data to travel from the input pin through the iff latch to the i output with no input delay programmed lv c m o s 2 5 (2) 0 xc3sd1800a 1.79 2.04 ns xc3sd3400a 1.65 2.11 ns t ioplid the time it takes for data to travel from the input pin through the iff latch to the i output with the input delay programmed lv c m o s 2 5 (2) 1 xc3sd1800a 2.23 2.47 ns 2 2.81 3.06 ns 3 3.39 3.86 ns 4 3.89 4.43 ns 5 3.83 4.39 ns 6 4.61 5.32 ns 7 5.40 6.24 ns 8 5.93 6.86 ns 1 xc3sd3400a 2.21 2.67 ns 2 2.71 3.25 ns 3 3.58 4.04 ns 4 4.15 4.62 ns 5 4.03 4.49 ns 6 4.57 5.31 ns 7 5.34 6.18 ns 8 5.84 6.78 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 2 6 and are based on the operating conditions set forth in ta b l e 7 and ta bl e 1 0 . 2. this propagation time requires adjustment whenever a signal st andard other than lvcmos25 is assigned to the data input. when this is true, add the appropriate input adjustment from ta bl e 2 2 . ta bl e 2 1 : propagation times for the iob input path (cont?d) symbol description conditions delay_value device speed grade units -5 -4 max max
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 26 input timing adjustments ta bl e 2 2 : input timing adjustments by iostandard convert input time from lvcmos25 to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4 single-ended standards lv t t l 0 . 6 2 0 . 6 2 n s lvcmos33 0.54 0.54 ns lvcmos25 0.00 0.00 ns lvcmos18 0.83 0.83 ns lvcmos15 0.60 0.60 ns lvcmos12 0.31 0.31 ns pci33_3 0.41 0.41 ns pci66_3 0.41 0.41 ns hstl_i 0.72 0.72 ns hstl_iii 0.77 0.77 ns hstl_i_18 0.69 0.69 ns hstl_ii_18 0.69 0.69 ns hstl_iii_18 0.79 0.79 ns sstl18_i 0.71 0.71 ns sstl18_ii 0.71 0.71 ns sstl2_i 0.68 0.68 ns sstl2_ii 0.68 0.68 ns sstl3_i 0.78 0.78 ns sstl3_ii 0.78 0.78 ns differential standards lv d s _ 2 5 0 . 7 6 0 . 7 6 n s lv d s _ 3 3 0 . 7 9 0 . 7 9 n s blvds_25 0.79 0.79 ns mini_lvds_25 0.78 0.78 ns mini_lvds_33 0.79 0.79 ns lvpecl_25 0.78 0.78 ns lvpecl_33 0.79 0.79 ns rsds_25 0.79 0.79 ns rsds_33 0.77 0.77 ns tmds_33 0.79 0.79 ns ppds_25 0.79 0.79 ns ppds_33 0.79 0.79 ns diff_hstl_i_18 0.74 0.74 ns diff_hstl_ii_18 0.72 0.72 ns diff_hstl_iii_18 1.05 1.05 ns diff_hstl_i 0.72 0.72 ns diff_hstl_iii 1.05 1.05 ns diff_sstl18_i 0.71 0.71 ns diff_sstl18_ii 0.71 0.71 ns diff_sstl2_i 0.74 0.74 ns diff_sstl2_ii 0.75 0.75 ns diff_sstl3_i 1.06 1.06 ns diff_sstl3_ii 1.06 1.06 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 2 6 and are based on the operating conditions set forth in ta bl e 7 , ta b l e 1 0 , and ta bl e 1 2 . 2. these adjustments are used to convert input path times originally specified for the lvcmos25 standard to times that correspond to other signal standards. ta b l e 2 2 : input timing adjustments by iostandard convert input time from lvcmos25 to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 27 output propagation times ta bl e 2 3 : timing for the iob output path symbol description conditions device speed grade units -5 -4 max max clock-to-output times t iockp when reading from the output flip-flop (off), the time from the active transition at the oclk input to data appearing at the output pin lv c m o s 2 5 (2) , 12 ma output drive, fast slew rate all 2.87 3.13 ns propagation times t ioop the time it takes for data to travel from the iob?s o input to the output pin lv c m o s 2 5 (2) , 12 ma output drive, fast slew rate all 2.78 2.91 ns set/reset times t iosrp time from asserting the off?s sr input to setting/resetting data at the output pin lv c m o s 2 5 (2) , 12 ma output drive, fast slew rate all 3.63 3.89 ns t iogsrq time from asserting the global set reset (gsr) input on the startup_spartan3a primitive to setting/resetting data at the output pin 8.62 9.65 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 2 6 and are based on the operating conditions set forth in ta b l e 7 and ta bl e 1 0 . 2. this time requires adjustment whenever a signal standard other than lvcmos25 with 12 ma drive and fast slew rate is assigned to the data output. when this is true, add the appropriate output adjustment from ta bl e 2 5 .
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 28 three-state output propagation times ta bl e 2 4 : timing for the iob three-state path symbol description conditions device speed grade units -5 -4 max max synchronous output enable/disable times t iockhz time from the active transition at the otclk input of the three-state flip-flop (tff) to when the output pin enters the high-impedance state lvcmos25, 12 ma output drive, fast slew rate all 1.13 1.39 ns t iockon (2) time from the active transition at tff?s otclk input to when the output pin drives valid data all 3.08 3.35 ns asynchronous output enable/disable times t gts time from asserting the global three state (gts) input on the startup_spartan3a primitive to when the output pin enters the high-impedance state lvcmos25, 12 ma output drive, fast slew rate all 9.47 10.36 ns set/reset times t iosrhz time from asserting tff?s sr input to when the output pin enters a high-impedance state lvcmos25, 12 ma output drive, fast slew rate all 1.61 1.86 ns t iosron (2) time from asserting tff?s sr input at tff to when the output pin drives valid data all 3.57 3.82 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 2 6 and are based on the operating conditions set forth in ta b l e 7 and ta bl e 1 0 . 2. this time requires adjustment whenever a signal standard other than lvcmos25 with 12 ma drive and fast slew rate is assigned to the data output. when this is true, add the appropriate output adjustment from ta bl e 2 5 .
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 29 output timing adjustments ta bl e 2 5 : output timing adjustments for iob convert output time from lvcmos25 with 12ma drive and fast slew rate to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4 single-ended standards lvttl slow 2 ma 5.58 5.58 ns 4 ma 3.16 3.16 ns 6 ma 3.17 3.17 ns 8 ma 2.09 2.09 ns 12 ma 1.62 1.62 ns 16 ma 1.24 1.24 ns 24 ma 2.74 (3) 2.74 (3) ns fast 2 ma 3.03 3.03 ns 4 ma 1.71 1.71 ns 6 ma 1.71 1.71 ns 8 ma 0.53 0.53 ns 12 ma 0.53 0.53 ns 16 ma 0.59 0.59 ns 24 ma 0.60 0.60 ns quietio 2 ma 27.67 27.67 ns 4 ma 27.67 27.67 ns 6 ma 27.67 27.67 ns 8 ma 16.71 16.71 ns 12 ma 16.67 16.67 ns 16 ma 16.22 16.22 ns 24 ma 12.11 12.11 ns lvcmos33 slow 2 ma 5.58 5.58 ns 4 ma 3.17 3.17 ns 6 ma 3.17 3.17 ns 8 ma 2.09 2.09 ns 12 ma 1.24 1.24 ns 16 ma 1.15 1.15 ns 24 ma 2.55 (3) 2.55 (3) ns fast 2 ma 3.02 3.02 ns 4 ma 1.71 1.71 ns 6 ma 1.72 1.72 ns 8 ma 0.53 0.53 ns 12 ma 0.59 0.59 ns 16 ma 0.59 0.59 ns 24 ma 0.51 0.51 ns quietio 2 ma 27.67 27.67 ns 4 ma 27.67 27.67 ns 6 ma 27.67 27.67 ns 8 ma 16.71 16.71 ns 12 ma 16.29 16.29 ns 16 ma 16.18 16.18 ns 24 ma 12.11 12.11 ns ta b l e 2 5 : output timing adjustments for iob (cont?d) convert output time from lvcmos25 with 12ma drive and fast slew rate to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 30 lvcmos25 slow 2 ma 5.33 5.33 ns 4 ma 2.81 2.81 ns 6 ma 2.82 2.82 ns 8 ma 1.14 1.14 ns 12 ma 1.10 1.10 ns 16 ma 0.83 0.83 ns 24 ma 2.26 (3) 2.26 (3) ns fast 2 ma 4.36 4.36 ns 4 ma 1.76 1.76 ns 6 ma 1.25 1.25 ns 8 ma 0.38 0.38 ns 12 ma 0.00 0.00 ns 16 ma 0.01 0.01 ns 24 ma 0.01 0.01 ns quietio 2 ma 25.92 25.92 ns 4 ma 25.92 25.92 ns 6 ma 25.92 25.92 ns 8 ma 15.57 15.57 ns 12 ma 15.59 15.59 ns 16 ma 14.27 14.27 ns 24 ma 11.37 11.37 ns ta bl e 2 5 : output timing adjustments for iob (cont?d) convert output time from lvcmos25 with 12ma drive and fast slew rate to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4 lvcmos18 slow 2 ma 4.48 4.48 ns 4 ma 3.69 3.69 ns 6 ma 2.91 2.91 ns 8 ma 1.99 1.99 ns 12 ma 1.57 1.57 ns 16 ma 1.19 1.19 ns fast 2 ma 3.96 3.96 ns 4 ma 2.57 2.57 ns 6 ma 1.90 1.90 ns 8 ma 1.06 1.06 ns 12 ma 0.83 0.83 ns 16 ma 0.63 0.63 ns quietio 2 ma 24.97 24.97 ns 4 ma 24.97 24.97 ns 6 ma 24.08 24.08 ns 8 ma 16.43 16.43 ns 12 ma 14.52 14.52 ns 16 ma 13.41 13.41 ns lvcmos15 slow 2 ma 5.82 5.82 ns 4 ma 3.97 3.97 ns 6 ma 3.21 3.21 ns 8 ma 2.53 2.53 ns 12 ma 2.06 2.06 ns fast 2 ma 5.23 5.23 ns 4 ma 3.05 3.05 ns 6 ma 1.95 1.95 ns 8 ma 1.60 1.60 ns 12 ma 1.30 1.30 ns quietio 2 ma 34.11 34.11 ns 4 ma 25.66 25.66 ns 6 ma 24.64 24.64 ns 8 ma 22.06 22.06 ns 12 ma 20.64 20.64 ns ta b l e 2 5 : output timing adjustments for iob (cont?d) convert output time from lvcmos25 with 12ma drive and fast slew rate to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 31 lvcmos12 slow 2 ma 7.14 7.14 ns 4 ma 4.87 4.87 ns 6 ma 5.67 5.67 ns fast 2 ma 6.77 6.77 ns 4 ma 5.02 5.02 ns 6 ma 4.09 4.09 ns quietio 2 ma 50.76 50.76 ns 4 ma 43.17 43.17 ns 6 ma 37.31 37.31 ns pci33_3 0.34 0.34 ns pci66_3 0.34 0.34 ns hstl_i 0.78 0.78 ns hstl_iii 1.16 1.16 ns hstl_i_18 0.35 0.35 ns hstl_ii_18 0.30 0.30 ns hstl_iii_18 0.47 0.47 ns sstl18_i 0.40 0.40 ns sstl18_ii 0.30 0.30 ns sstl2_i 0.00 0.00 ns sstl2_ii ?0.05 ?0.05 ns sstl3_i 0.00 0.00 ns sstl3_ii 0.17 0.17 ns ta bl e 2 5 : output timing adjustments for iob (cont?d) convert output time from lvcmos25 with 12ma drive and fast slew rate to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4 differential standards lvds_25 1.16 1.16 ns lvds_33 0.46 0.46 ns blvds_25 0.11 0.11 ns mini_lvds_25 0.75 0.75 ns mini_lvds_33 0.40 0.40 ns lvpecl_25 inputs only lvpecl_33 rsds_25 1.42 1.42 ns rsds_33 0.58 0.58 ns tmds_33 0.46 0.46 ns ppds_25 1.07 1.07 ns ppds_33 0.63 0.63 ns diff_hstl_i_18 0.43 0.43 ns diff_hstl_ii_18 0.41 0.41 ns diff_hstl_iii_18 0.36 0.36 ns diff_hstl_i 1.01 1.01 ns diff_hstl_iii 0.54 0.54 ns diff_sstl18_i 0.49 0.49 ns diff_sstl18_ii 0.41 0.41 ns diff_sstl2_i 0.82 0.82 ns diff_sstl2_ii 0.09 0.09 ns diff_sstl3_i 1.16 1.16 ns diff_sstl3_ii 0.28 0.28 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 2 6 and are based on the operating conditions set forth in ta bl e 7 , ta b l e 1 0 , and ta bl e 1 2 . 2. these adjustments are used to convert output- and three-state-path times originally specified for the lvcmos25 standard with 12 ma drive and fast slew rate to times that correspond to other signal standards. do not adjust times that measure when outputs go into a high-impedance state. 3. note that 16 ma drive is faster than 24 ma drive for the slow slew rate. ta b l e 2 5 : output timing adjustments for iob (cont?d) convert output time from lvcmos25 with 12ma drive and fast slew rate to the following signal standard (iostandard) add the adjustment below units speed grade -5 -4
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 32 timing measurem ent methodology when measuring timing parameters at the programmable i/os, different signal standards call for different test conditions. ta b l e 2 6 lists the conditions to use for each standard. the method for measuring input timing is as follows: a signal that swings between a low logic level of v l and a high logic level of v h is applied to the input under test. some standards also require the application of a bias voltage to the v ref pins of a given bank to properly set the input-switching threshold. the measurement point of the input signal (v m ) is commonly located halfway between v l and v h . the output test setup is shown in figure 8 . a termination voltage v t is applied to the termination resistor r t , the other end of which is connected to the output. for each standard, r t and v t generally take on the standard values recommended for minimizing signal reflections. if the standard does not ordinarily use terminations (for example, lvcmos, lvttl), then r t is set to 1m to indicate an open connection, and v t is set to zero. the same measurement point (v m ) that was used at the input is also used at the output. x-ref target - figure 8 figure 8: output test setup fpga output v t (v ref ) r t (r ref ) v m (v meas ) c l (c ref ) ds312-3_04_102406 notes: 1. the names shown in parentheses are used in the ibis file. ta bl e 2 6 : test methods for timing measurement at i/os signal standard (iostandard) inputs outputs (2) inputs and outputs v ref (v) v l (v) v h (v) r t ( )v t (v) v m (v) single-ended lv t t l ? 0 3.3 1m 0 1.4 lv c m o s 3 3 ? 0 3.3 1m 0 1.65 lv c m o s 2 5 ? 0 2.5 1m 0 1.25 lv c m o s 1 8 ? 0 1.8 1m 0 0.9 lv c m o s 1 5 ? 0 1.5 1m 0 0.75 lv c m o s 1 2 ? 0 1.2 1m 0 0.6 pci33_3 rising ?note 3 note 3 25 0 0.94 falling 25 3.3 2.03 pci66_3 rising ?note 3 note 3 25 0 0.94 falling 25 3.3 2.03 hstl_i 0.75 v ref ? 0.5 v ref + 0.5 50 0.75 v ref hstl_iii 0.9 v ref ? 0.5 v ref + 0.5 50 1.5 v ref hstl_i_18 0.9 v ref ? 0.5 v ref + 0.5 50 0.9 v ref hstl_ii_18 0.9 v ref ? 0.5 v ref + 0.5 25 0.9 v ref hstl_iii_18 1.1 v ref ? 0.5 v ref + 0.5 50 1.8 v ref sstl18_i 0.9 v ref ? 0.5 v ref + 0.5 50 0.9 v ref sstl18_ii 0.9 v ref ? 0.5 v ref + 0.5 25 0.9 v ref sstl2_i 1.25 v ref ? 0.75 v ref + 0.75 50 1.25 v ref sstl2_ii 1.25 v ref ? 0.75 v ref + 0.75 25 1.25 v ref sstl3_i 1.5 v ref ? 0.75 v ref + 0.75 50 1.5 v ref sstl3_ii 1.5 v ref ? 0.75 v ref + 0.75 25 1.5 v ref
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 33 the capacitive load (c l ) is connected between the output and gnd. the output timing for all standards, as published in the speed files and the data sheet, is always based on a c l value of zero. high-impedance probes (less than 1 pf) are used for all measurements. any delay that the test fixture might contribute to test measurements is subtracted from those measurements to produce the final timing numbers as published in the speed files and data sheet. differential lvds_25 ?v icm ? 0.125 v icm + 0.125 50 1.2 v icm lvds_33 ?v icm ? 0.125 v icm + 0.125 50 1.2 v icm blvds_25 ?v icm ? 0.125 v icm + 0.125 1m 0 v icm mini_lvds_25 ?v icm ? 0.125 v icm + 0.125 50 1.2 v icm mini_lvds_33 ?v icm ? 0.125 v icm + 0.125 50 1.2 v icm lvpecl_25 ?v icm ? 0.3 v icm + 0.3 n/a n/a v icm lvpecl_33 ?v icm ? 0.3 v icm + 0.3 n/a n/a v icm rsds_25 ?v icm ? 0.1 v icm + 0.1 50 1.2 v icm rsds_33 ?v icm ? 0.1 v icm + 0.1 50 1.2 v icm tmds_33 ?v icm ? 0.1 v icm + 0.1 50 3.3 v icm ppds_25 ?v icm ? 0.1 v icm + 0.1 50 0.8 v icm ppds_33 ?v icm ? 0.1 v icm + 0.1 50 0.8 v icm diff_hstl_i_18 ?v icm ? 0.5 v icm + 0.5 50 0.9 v icm diff_hstl_ii_18 ?v icm ? 0.5 v icm + 0.5 50 0.9 v icm diff_hstl_iii_18 ?v icm ? 0.5 v icm + 0.5 50 1.8 v icm diff_hstl_i ?v icm ? 0.5 v icm + 0.5 50 0.9 v icm diff_hstl_iii ?v icm ? 0.5 v icm + 0.5 50 0.9 v icm diff_sstl18_i ?v icm ? 0.5 v icm + 0.5 50 0.9 v icm diff_sstl18_ii ?v icm ? 0.5 v icm + 0.5 50 0.9 v icm diff_sstl2_i ?v icm ? 0.5 v icm + 0.5 50 1.25 v icm diff_sstl2_ii ?v icm ? 0.5 v icm + 0.5 50 1.25 v icm diff_sstl3_i ?v icm ? 0.5 v icm + 0.5 50 1.5 v icm diff_sstl3_ii ?v icm ? 0.5 v icm + 0.5 50 1.5 v icm notes: 1. descriptions of the relevant symbols are: v ref ? the reference voltage for setting the input switching threshold v icm ? the common mode input voltage v m ? voltage of measurement point on signal transition v l ? low-level test voltage at input pin v h ? high-level test voltage at input pin r t ? effective termination resistance, which takes on a value of 1 m when no parallel termination is required v t ? termination voltage 2. the load capacitance (c l ) at the output pin is 0 pf for all signal standards. 3. according to the pci specification. for information on pci ip solutions, see www.xilinx.com/pci . the pcix iostandard is available and has equivalent characteristics but no pci-x ip is supported. ta bl e 2 6 : test methods for timing measurement at i/os (cont?d) signal standard (iostandard) inputs outputs (2) inputs and outputs v ref (v) v l (v) v h (v) r t ( )v t (v) v m (v)
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 34 using ibis models to simulate load conditions in application ibis models permit the most accurate prediction of timing delays for a given application. the parameters found in the ibis model (v ref , r ref , and v meas ) correspond directly with the parameters used in ta b l e 2 6 (v t , r t , and v m ). do not confuse v ref (the termination voltage) from the ibis model with v ref (the input-switching threshold) from the table. a fourth parameter, c ref , is always zero. the four parameters describe all relevant output test conditions. ibis models are found in the xilinx development software as well as at the following link: www.xilinx.com/support/download/index.htm delays for a given application are simulated according to its specific load conditions as follows: 1. simulate the desired signal standard with the output driver connected to the test setup shown in figure 8 . use parameter values v t , r t , and v m from ta bl e 2 6 . c ref is zero. 2. record the time to v m . 3. simulate the same signal standard with the output driver connected to the pcb trace with load. use the appropriate ibis model (including v ref , r ref , c ref , and v meas values) or capacitive value to represent the load. 4. record the time to v meas . 5. compare the results of steps 2 and 4. add (or subtract) the increase (or decrease) in delay to (or from) the appropriate output standard adjustment ( ta b l e 2 5 ) to yield the worst-case delay of the pcb trace. simultaneously switching output guidelines this section provides guidelines for the recommended maximum allowable number of simultaneous switching outputs (ssos). these guidelines describe the maximum number of user i/o pins of a given output signal standard that should simultaneously swit ch in the same direction, while maintaining a safe level of switching noise. meeting these guidelines for the stated test conditions ensures that the fpga operates free from the adverse effects of ground and power bounce. ground or power bounce occurs when a large number of outputs simultaneously switch in the same direction. the output drive transistors all conduct current to a common voltage rail. low-to-high tr ansitions conduct to the v cco rail; high-to-low transitions conduct to the gnd rail. the resulting cumulative current transient induces a voltage difference across the inductance that exists between the die pad and the power supply or ground return. the inductance is associated with bonding wires, the package lead frame, and any other signal routing inside the package. other variables contribute to sso noise levels, including stray inductance on the pcb as well as capacitive loading at receivers. any sso-induced voltage consequently affects internal switching noise margins and ultimately signal quality. ta b l e 2 7 and ta bl e 2 8 provide the essential sso guidelines. for each device/package combination, ta b l e 2 7 provides the number of equivalent v cco /gnd pairs. the equivalent number of pairs is based on characterization and may not match the physical number of pairs. for each output signal standard and drive strength, ta b l e 2 8 recommends the maximum number of ssos, switching in the same direction, allowed per v cco /gnd pair within an i/o bank. the guidelines in ta bl e 2 8 are categorized by package style, slew rate, and output drive current. furthermore, the number of ssos is specified by i/o bank. generally, the left and right i/o banks (banks 1 and 3) support higher output drive current. multiply the appropriate numbers from ta bl e 2 7 and ta b l e 2 8 to calculate the maximum number of ssos allowed within an i/o bank. exceeding these sso guidelines might result in increased power or ground bounce, degraded signal integrity, or increased system jitter. sso max /io bank = ta b l e 2 7 x ta bl e 2 8 the recommended maximum sso values assumes that the fpga is soldered on the printed circuit board and that the board uses sound design practices. the sso values do not apply for fpgas mounted in sockets, due to the lead inductance introduced by the socket. the sso values assume that the v ccaux is powered at 3.3v. setting v ccaux to 2.5v provides better sso characteristics. ta b l e 2 7 : equivalent v cco /gnd pairs per bank device package style (including pb-free) cs484 fg676 xc3sd1800a 6 9 xc3sd3400a 6 10
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 35 ta bl e 2 8 : recommended simultaneously switching outputs per v cco /gnd pair (v ccaux =3.3v) signal standard (iostandard) package type cs484, fg676 top, bottom (banks 0, 2) left, right (banks 1, 3) single-ended standards lvttl slow 2 60 60 441 41 629 29 822 22 12 13 13 16 11 11 24 9 9 fast 2 10 10 46 6 65 5 83 3 12 3 3 16 3 3 24 2 2 quietio 2 80 80 448 48 636 36 827 27 12 16 16 16 13 13 24 12 12 lv c m o s 3 3 s l ow 2 7 6 7 6 446 46 627 27 820 20 12 13 13 16 10 10 24 ?9 fast 2 10 10 48 8 65 5 84 4 12 4 4 16 2 2 24 ?2 quietio 2 76 76 446 46 632 32 826 26 12 18 18 16 14 14 24 ?10 ta b l e 2 8 : recommended simultaneously switching outputs per v cco /gnd pair (v ccaux =3.3v) (cont?d) signal standard (iostandard) package type cs484, fg676 top, bottom (banks 0, 2) left, right (banks 1, 3)
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 36 lv c m o s 2 5 s l ow 2 7 6 7 6 446 46 633 33 824 24 12 18 18 16 ?11 24 ?7 fast 2 18 18 414 14 66 6 86 6 12 3 3 16 ?3 24 ?2 quietio 2 76 76 460 60 648 48 836 36 12 36 36 16 ?36 24 ?8 ta bl e 2 8 : recommended simultaneously switching outputs per v cco /gnd pair (v ccaux =3.3v) (cont?d) signal standard (iostandard) package type cs484, fg676 top, bottom (banks 0, 2) left, right (banks 1, 3) lv c m o s 1 8 s l ow 2 6 4 6 4 434 34 622 22 818 18 12 ?13 16 ?10 fast 2 18 18 49 9 67 7 84 4 12 ?4 16 ?3 quietio 2 64 64 464 64 648 48 836 36 12 ?36 16 ?24 lv c m o s 1 5 s l ow 2 5 5 5 5 431 31 618 18 8 ?15 12 ?10 fast 2 25 25 410 10 66 6 8 ?4 12 ?3 quietio 2 70 70 440 40 631 31 8 ?31 12 ?20 ta b l e 2 8 : recommended simultaneously switching outputs per v cco /gnd pair (v ccaux =3.3v) (cont?d) signal standard (iostandard) package type cs484, fg676 top, bottom (banks 0, 2) left, right (banks 1, 3)
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 37 lv c m o s 1 2 s l ow 2 4 0 4 0 4 ?25 6 ?18 fast 2 31 31 4 ?13 6 ?9 quietio 2 55 55 4 ?36 6 ?36 pci33_3 16 16 pci66_3 ?13 hstl_i ?20 hstl_iii ?8 hstl_i_18 17 17 hstl_ii_18 ?5 hstl_iii_18 10 8 sstl18_i 7 15 sstl18_ii ?9 sstl2_i 18 18 sstl2_ii ?9 sstl3_i 8 10 sstl3_ii 6 7 ta bl e 2 8 : recommended simultaneously switching outputs per v cco /gnd pair (v ccaux =3.3v) (cont?d) signal standard (iostandard) package type cs484, fg676 top, bottom (banks 0, 2) left, right (banks 1, 3) differential standards (number of i/o pairs or channels) lv d s _ 2 5 2 2 ? lv d s _ 3 3 2 7 ? blvds_25 4 4 mini_lvds_25 22 ? mini_lvds_33 27 ? lvpecl_25 inputs only lvpecl_33 inputs only rsds_25 22 ? rsds_33 27 ? tmds_33 27 ? ppds_25 22 ? ppds_33 27 ? diff_hstl_i_18 8 8 diff_hstl_ii_18 ?2 diff_hstl_iii_18 5 4 diff_hstl_i ?10 diff_hstl_iii ?4 diff_sstl18_i 3 7 diff_sstl18_ii ?4 diff_sstl2_i 9 9 diff_sstl2_ii ?4 diff_sstl3_i 4 5 diff_sstl3_ii 3 3 notes: 1. not all i/o standards are supported on all i/o banks. the left and right banks (i/o banks 1 and 3) support higher output drive current than the top and bottom banks (i/o banks 0 and 2). similarly, true differential output standards, such as lvds, rsds, ppds, minilvds, and tmds, are only supported in top or bottom banks (i/o banks 0 and 2). refer to ug331 : spartan-3 generation fpga user guide for additional information. 2. the numbers in this table are recommendations that assume sound board lay out practice. this table assumes the following parasitic factors: combined pcb trace and land inductance per v cco and gnd pin of 1.0 nh, receiver capacitive load of 15 pf. test limits are the v il /v ih voltage limits for the respective i/o standard. 3. if more than one signal standard is assigned to the i/os of a given bank, refer to xapp689 : managing ground bounce in large fpgas for information on how to perform weighted average sso calculations. ta b l e 2 8 : recommended simultaneously switching outputs per v cco /gnd pair (v ccaux =3.3v) (cont?d) signal standard (iostandard) package type cs484, fg676 top, bottom (banks 0, 2) left, right (banks 1, 3)
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 38 configurable logic block (clb) timing ta bl e 2 9 : clb (slicem) timing symbol description speed grade units -5 -4 min max min max clock-to-output times t cko when reading from the ffx (ffy) flip-flop, the time from the active transition at the clk input to data appearing at the xq (yq) output ?0.60 ?0.68ns setup times t as time from the setup of data at the f or g input to the active transition at the clk input of the clb 0.18 ?0.36 ?ns t dick time from the setup of data at the bx or by input to the active transition at the clk input of the clb 1.58 ?1.88 ?ns hold times t ah time from the active transition at the clk input to the point where data is last held at the f or g input 0.00 ?0.00 ?ns t ckdi time from the active transition at the clk input to the point where data is last held at the bx or by input 0.00 ?0.00 ?ns clock timing t ch the high pulse width of the clb?s clk signal 0.63 ?0.75 ?ns t cl the low pulse width of the clk signal 0.63 ?0.75 ?ns f tog toggle frequency (for export control) 0 770 0 667 mhz propagation times t ilo the time it takes for data to travel from the clb?s f (g) input to the x (y) output ?0.62 ?0.71ns set/reset pulse width t rpw_clb the minimum allowable pulse width, high or low, to the clb?s sr input 1.33 ?1.61 ?ns notes: 1. the numbers in this table are based on the operating conditions set forth in ta b l e 7 .
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 39 ta bl e 3 0 : clb distributed ram swit ching characteristics symbol description speed grade units -5 -4 min max min max clock-to-output times t shcko time from the active edge at the clk input to data appearing on the distributed ram output ?1.44 ?1.72ns setup times t ds setup time of data at the bx or by input before the active transition at the clk input of the distributed ram ?0.07 ? ?0.02 ?ns t as setup time of the f/g address inputs before the active transition at the clk input of the distributed ram 0.18 ?0.36 ?ns t ws setup time of the write enable input before the active transition at the clk input of the distributed ram 0.30 ?0.59 ?ns hold times t dh hold time of the bx and by data inputs after the active transition at the clk input of the distributed ram 0.13 ?0.13 ?ns t ah, t wh hold time of the f/g address inputs or the write enable input after the active transition at the clk input of the distributed ram 0.01 ?0.01 ?ns clock pulse width t wph , t wpl minimum high or low pulse width at clk input 0.88 ?1.01 ?ns ta bl e 3 1 : clb shift register switching characteristics symbol description speed grade units -5 -4 min max min max clock-to-output times t reg time from the active edge at the clk input to data appearing on the shift register output ?4.11 ?4.82ns setup times t srlds setup time of data at the bx or by input before the active transition at the clk input of the shift register 0.13 ?0.18 ?ns hold times t srldh hold time of the bx or by data input after the active transition at the clk input of the shift register 0.16 ?0.16 ?ns clock pulse width t wph , t wpl minimum high or low pulse width at clk input 0.90 ?1.01 ?ns
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 40 clock buffer/multiplexer switching characteristics ta bl e 3 2 : clock distribution swit ching characteristics symbol description minimum maximum units speed grade -5 -4 t gio global clock buffer (bufg, bufgmux, bufgce) i input to o-output delay ?0.220.23ns t gsi global clock multiplexer (bufgmux) select s-input setup to i0 and i1 inputs. same as bufgce enable ce-input ?0.560.63ns f bufg frequency of signals distributed on global buffers (all sides) 0 350 334 mhz notes: 1. the numbers in this table are based on the operating conditions set forth in ta b l e 7 .
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 41 block ram timing ta bl e 3 3 : block ram timing symbol description speed grade units -5 -4 min max min max clock-to-output times t rcko_doa_nc when reading from block ram, the delay from the active transition at the clk input to data appearing at the dout output ?2.38 ?2.80ns t rcko_doa clock clk to dout output (with output register) ?1.24 ?1.45ns setup times t rcck_addr setup time for the addr inputs before the active transition at the clk input of the block ram 0.40 ?0.46 ?ns t rdck_dib setup time for data at the din inputs before the active transition at the clk input of the block ram 0.29 ?0.33 ?ns t rcck_enb setup time for the en input before t he active transition at the clk input of the block ram 0.51 ?0.60 ?ns t rcck_web setup time for the we input before the active transition at the clk input of the block ram 0.64 ?0.75 ?ns t rcck_regce setup time for the ce input before t he active transition at the clk input of the block ram 0.34 ?0.40 ?ns t rcck_rst setup time for the rst input before the active transition at the clk input of the block ram 0.22 ?0.25 ?ns hold times t rckc_addr hold time on the addr inputs after the active transition at the clk input 0.09 ?0.10 ?ns t rckc_dib hold time on the din inputs after the active transition at the clk input 0.09 ?0.10 ?ns t rckc_enb hold time on the en input after the active transition at the clk input 0.09 ?0.10 ?ns t rckc_web hold time on the we input after the ac tive transition at the clk input 0.09 ?0.10 ?ns t rckc_regce hold time on the ce input after the active transition at the clk input 0.09 ?0.10 ?ns t rckc_rst hold time on the rst input after the active transition at the clk input 0.09 ?0.10 ?ns clock timing t bpwh high pulse width of the clk signal 1.56 ?1.79 ?ns t bpwl low pulse width of the clk signal 1.56 ?1.79 ?ns clock frequency f bram block ram clock frequency 0 320 0 280 mhz notes: 1. the numbers in this table are based on the operating conditions set forth in ta b l e 7 .
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 42 dsp48a timing to reference the dsp48a block diagram, see ug431 : xtremedsp dsp48a for spartan-3a dsp fpga user guide . ta bl e 3 4 : setup times for the dsp48a symbol description pre-adder multiplier post-adder speed grade units -5 -4 min min setup times of data/control pins to the input register clock t dspdck_aa a input to a register clk ? ? ? 0.04 0.04 ns t dspdck_db d input to b register clk yes ? ? 1.64 1.88 ns t dspdck_cc c input to c register clk ? ? ? 0.05 0.05 ns t dspdck_dd d input to d register clk ? ? ? 0.04 0.04 ns t dspdck_opb opmode input to b register clk yes ? ? 0.37 0.42 ns t dspdck_opop opmode input to opmode register clk ? ? ? 0.06 0.06 ns setup times of data pins to the pipeline register clock t dspdck_am a input to m register clk ?yes ? 3.30 3.79 ns t dspdck_bm b input to m register clk yes yes ? 4.33 4.97 ns no yes ? 3.30 3.79 ns t dspdck_dm d input to m register clk yes yes ? 4.41 5.06 ns t dspdck_opm opmode to m register clk yes yes ? 4.72 5.42 ns setup times of data/control pins to the output register clock t dspdck_ap a input to p register clk ? yes yes 4.78 5.49 ns t dspdck_bp b input to p register clk yes yes yes 5.87 6.74 ns no yes yes 4.77 5.48 ns t dspdck_dp d input to p register clk yes yes yes 5.95 6.83 ns t dspdck_cp c input to p register clk ? ? yes 1.90 2.18 ns t dspdck_opp opmode input to p regist er clk yes yes yes 6.25 7.18 ns notes: 1. "yes" means that the component is in the path. "no" means that the component is being bypassed. ??? means that no path exists , so it is not applicable. 2. the numbers in this table are based on the operating conditions set forth in ta b l e 7 .
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 43 ta bl e 3 5 : clock to out, propagation delays, and maximum frequency for the dsp48a symbol description pre-adder multiplier post-adder speed grade units -5 -4 max max clock to out from output re gister clock to output pin t dspcko_pp clk (preg) to p output ? ? ? 1.26 1.44 ns clock to out from pipeline register clock to output pins t dspcko_pm clk (mreg) to p output ? yes yes 3.16 3.63 ns ? yes no 1.94 2.23 ns clock to out from input regi ster clock to output pins t dspcko_pa clk (areg) to p output ? yes yes 6.33 7.27 ns t dspcko_pb clk (breg) to p output yes yes yes 7.45 8.56 ns t dspcko_pc clk (creg) to p output ? ? yes 3.37 3.87 ns t dspcko_pd clk (dreg) to p output yes yes yes 7.33 8.42 ns combinatorial delays from input pins to output pins t dspdo_ap t dspdo_bp a or b input to p output ? no yes 2.78 3.19 ns ? yes no 4.60 5.28 ns ? yes yes 5.65 6.49 ns t dspdo_bp b input to p output yes no no 3.49 4.01 ns yes yes no 5.79 6.65 ns ye s ye s ye s 6 . 7 4 7 . 7 4 n s t dspdo_cp c input to p output ? ? yes 2.76 3.17 ns t dspdo_dp d input to p output yes yes yes 6.81 7.82 ns t dspdo_opp opmode input to p output yes yes yes 7.12 8.18 ns maximum frequency f max all registers used yes yes yes 287 250 mhz notes: 1. to reference the dsp48a block diagram, see ug431 : xtremedsp dsp48a for spartan-3a dsp fpga user guide . 2. "yes" means that the component is in the path. "no" means that the component is being bypassed. ??? means that no path exists , so it is not applicable. 3. the numbers in this table are based on the operating conditions set forth in ta b l e 7 .
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 44 digital clock manager (dcm) timing for specification purposes, the dcm consists of three key components: the delay-locked loop (dll), the digital frequency synthesizer (dfs), and the phase shifter (ps). aspects of dll operation play a role in all dcm applications. all such applicat ions inevitably use the clkin and the clkfb inputs connected to either the clk0 or the clk2x feedback, respectively. thus, specifications in the dll tables ( ta bl e 3 6 and ta bl e 3 7 ) apply to any application that only employs the dll component. when the dfs and/or the ps components are used together with the dll, then the specifications listed in the dfs and ps tables ( ta bl e 3 8 through ta b l e 4 1 ) supersede any corresponding ones in the dll tables. dll specifications that do not change with the addition of dfs or ps functions are presented in ta bl e 3 6 and ta bl e 3 7 . period jitter and cycle-cycle jitter are two of many different ways of specifying clock jitter. both specifications describe statistical variation from a mean value. period jitter is the worst-case deviation from the ideal clock period over a collection of millions of samples. in a histogram of period jitter, the mean value is the clock period. cycle-cycle jitter is the worst-ca se difference in clock period between adjacent clock cycles in the collection of clock periods sampled. in a histogram of cycle-cycle jitter, the mean value is zero. spread spectrum dcms accept typical spread spectrum clocks as long as they meet the input requir ements. the dll will track the frequency changes created by th e spread spectrum clock to drive the global clocks to the fpga logic. see xapp469 : spread-spectrum clocking reception for displays for details. delay-locked loop (dll) ta bl e 3 6 : recommended operating conditions for the dll symbol description speed grade units -5 -4 min max min max input frequency ranges f clkin clkin_freq_dll frequency of the clkin clock input 5 (2) 280 (3) 5 (2) 250 (3) mhz input pulse requirements clkin_pulse clkin pulse width as a percentage of the clkin period f clkin < 150 mhz 40% 60% 40% 60% ? f clkin > 150 mhz 45% 55% 45% 55% ? input clock jitter tolerance and delay path variation (4) clkin_cyc_jitt_dll _lf cycle-to-cycle jitter at the clkin input f clkin < 150 mhz ?300 ?300ps clkin_cyc_jitt_dll_hf f clkin > 150 mhz ?150 ?150ps clkin_per_jitt_dll period jitter at the clkin input ?1 ?1ns clkfb_delay_var_ext allowable variation of off-chip feedback delay from the dcm output to the clkfb input ?1 ?1ns notes: 1. dll specifications apply when any of the dll outputs (clk0, clk90, clk180, clk270, clk2x, clk2x180, or clkdv) are in use. 2. the dfs, when operating independently of the dll, supports lower fclkin frequencies. see ta b l e 3 8 . 3. to support double the maximum effective fclkin limit, set the clkin_divide_by_2 attribute to true. this attribute divides the incoming clock frequency by two as it enters the dcm. the clk2x output reproduces the clock frequency provided on the clkin input. 4. clkin input jitter beyond these limits might cause the dcm to lose lock. 5. the dcm specifications are guaranteed when both adjacent dcms are locked.
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 45 ta bl e 3 7 : switching characteristics for the dll symbol description device speed grade units -5 -4 min max min max output frequency ranges clkout_freq_clk0 frequency for the clk0 and clk180 outputs all 5 280 5 250 mhz clkout_freq_clk90 frequency for the clk90 and clk270 outputs 5 200 5 200 mhz clkout_freq_2x frequency for the clk2x and clk2x180 outputs 10 334 10 334 mhz clkout_freq_dv frequency for the clkdv output 0.3125 186 0.3125 166 mhz output clock jitter (2)(3)(4) clkout_per_jitt_0 period jitter at the clk0 output all ?100 ?100ps clkout_per_jitt_90 period jitter at the clk90 output ?150 ?150ps clkout_per_jitt_180 period jitter at the clk180 output ?150 ?150ps clkout_per_jitt_270 period jitter at the clk270 output ?150 ?150ps clkout_per_jitt_2x period jitter at the clk2x and clk2x180 outputs ? [0.5% of clkin period + 100] ? [0.5% of clkin period + 100] ps clkout_per_jitt_dv1 period jitter at the clkdv output when performing integer division ?150 ?150ps clkout_per_jitt_dv2 period jitter at the clkdv output when performing non-integer division ? [0.5% of clkin period + 100] ? [0.5% of clkin period + 100] ps duty cycle (4) clkout_duty_cycle_ dll duty cycle variation for t he clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv outputs, including the bufgmux an d clock tree duty-cycle distortion all ?[1% of clkin period + 350] ?[1% of clkin period + 350] ps phase alignment (4) clkin_clkfb_phase phase offset betw een the clkin and clkfb inputs all ?150 ?150ps clkout_phase_dll phase offset between dll outputs clk0 to clk2x (not clk2x180) ?[1% of clkin period + 100] ?[1% of clkin period + 100] ps all others ?[1% of clkin period + 150] ?[1% of clkin period + 150] ps lock time lock_dll (3) when using the dll alone: the time from deassertion at the dcm?s reset input to the rising transition at its locked output. when the dcm is locked, the clkin and clkfb signals are in phase 5 mhz < fclkin < 15 mhz all ?5 ?5ms fclkin > 15 mhz ? 600 ? 600 s
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 46 digital frequency synthesizer (dfs) delay lines dcm_delay_step (5) finest delay resolution, averaged over all steps all 15 35 15 35 ps notes: 1. the numbers in this table are based on the operating conditions set forth in ta b l e 7 and ta bl e 3 6 . 2. indicates the maximum amount of output jitter that the dcm adds to the jitter on the clkin input. 3. for optimal jitter tolerance and faster lock time, use the clkin_period attribute. 4. some jitter and duty-cycle specifications include 1% of input clock period or 0.01 ui. for example, the data sheet specifies a maximum jitter of [1% of clkin period + 150]. assume the clkin frequency is 100 mhz. the equivalent clkin period is 10 ns and 1% of 10 ns is 0. 1ns or 100 ps. according to the data sheet, the maximum jitter is [100 ps + 150 ps] = 250 ps, averaged over all steps. 5. the typical delay step size is 23 ps. ta bl e 3 8 : recommended operating conditions for the dfs symbol description speed grade units -5 -4 min max min max input frequency ranges (2) f clkin clkin_freq_fx frequency for the clkin input 0.2 333 (5) 0.2 333 (5) mhz input clock jitter tolerance (3) clkin_cyc_jitt_fx_lf cycle-to-cycle jitter at the clkin input, based on clkfx output frequency f clkfx < 150 mhz ?300 ?300ps clkin_cyc_jitt_fx_hf f clkfx > 150 mhz ?150 ?150ps clkin_per_jitt_fx period jitter at the clkin input ?1 ?1ns notes: 1. dfs specifications apply when either of th e dfs outputs (clkfx or clkfx180) are used. 2. if both dfs and dll outputs are used on the same dcm, follow the more restrictive clkin_freq_dll specifications in ta bl e 3 6 . 3. clkin input jitter beyond these limits may cause the dcm to lose lock. 4. the dcm specifications are guaranteed when both adjacent dcms are locked. 5. to support double the maximum effective f clkin limit, set the clkin_divide_by_2 attribute to true. this attribute divides the incoming clock frequency by two as it enters the dcm. ta bl e 3 7 : switching characteristics for the dll (cont?d) symbol description device speed grade units -5 -4 min max min max
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 47 ta bl e 3 9 : switching characteristics for the dfs symbol description device speed grade units -5 -4 min max min max output frequency ranges clkout_freq_fx (2) frequency for the clkfx and clkfx180 outputs all 5 350 5 311 mhz output clock jitter (3)(4) clkout_per_jitt_fx period jitter at the clkfx and clkfx180 outputs. clkin 20 mhz all typ max typ max use the spartan-3a jitter calculator: www.xilinx.com/support/documentation/ data_sheets/s3a_jitter_calc.zip ps clkin > 20 mhz [1% of clkfx period + 100] [1% of clkfx period + 200] [1% of clkfx period + 100] [1% of clkfx period + 200] ps duty cycle (5)(6) clkout_duty_cycle_ fx duty cycle precision for the clkfx and clkfx180 outputs, including the bufgmux and clock tree duty-cycle distortion all ?[1% of clkfx period + 350] ?[1% of clkfx period + 350] ps phase alignment (6) clkout_phase_fx phase offset bet ween the dfs clkf x output and the dll clk0 output when both the dfs and dll are used all ?200 ?200ps clkout_phase_fx180 phase offset bet ween the dfs clkfx 180 output and the dll clk0 output when both the dfs and dll are used all ?[1% of clkfx period + 200] ?[1% of clkfx period + 200] ps lock time lock_fx (2)(3) the time from deassertion at the dcm?s reset input to the rising transition at its locked output. the dfs asserts locked when the clkfx and clkfx180 signals are valid. if using both the dll and the dfs, use the longer locking time. 5 mhz < f clkin < 15 mhz all ?5 ?5ms f clkin > 15 mhz ? 450 ? 450 s notes: 1. the numbers in this table are based on the operating conditions set forth in ta b l e 7 and ta bl e 3 8 . 2. dfs performance requires the additional logic automatically added by ise 9.1i and later software revisions. 3. for optimal jitter tolerance and faster lock time, use the clkin_period attribute. 4. maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 ssos and 25% clb switching) on an fpga. output jitter strongly depends on the environment, in cluding the number of ssos, the output drive strength, clb uti lization, clb switching activities, switching frequency, power supply and pcb design. the actual maximum output jitter depends on the sys tem application. 5. the clkfx and clkfx180 outputs always have an approximate 50% duty cycle. 6. some duty-cycle and alignment specifications include a percentage of the clkfx output period. for example, the data sheet spe cifies a maximum clkfx jitter of ?[1% of clkfx period + 200]?. assume the clkfx output frequency is 100 mhz. the equivalent clkfx perio d is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. according to the data sheet, the maximum jitter is [100 ps + 200 ps] = 300 ps.
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 48 phase shifter (ps) miscellaneous dcm timing ta bl e 4 0 : recommended operating conditions for the ps in variable phase mode symbol description speed grade units -5 -4 min max min max operating frequency ranges psclk_freq (fpsclk) frequency for the psclk input 1 167 1 167 mhz input pulse requirements psclk_pulse psclk pulse width as a pe rcentage of the psclk period 40% 60% 40% 60% ? ta bl e 4 1 : switching characteristics for the ps in variable phase mode symbol description phase shift amount units phase shifting range max_steps (2,3) maximum allowed number of dcm_delay_step steps for a given clkin clock period, where t = clkin clock period in ns. if using clkin_divide_by_2 = true, double the effective clock period. clkin < 60 mhz [integer(10 ? (t clkin ? 3 ns))] steps clkin 60 mhz [integer(15 ? (t clkin ? 3 ns))] fine_shift_range_min minimum guarante ed delay for variable phase shifting [max_steps ? dcm_delay_step_min] ns fine_shift_range_max maximum guaranteed delay for variable phase shifting [max_steps ? dcm_delay_step_max] ns notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 7 and ta b l e 4 0 . 2. the maximum variable phase shift range, max_steps, is only valid when the dcm is has no initial fixed phase shifting, that is , the phase_shift attribute is set to 0. 3. the dcm_delay_step values are provided at the bottom of ta bl e 3 7 . ta bl e 4 2 : miscellaneous dcm timing symbol description min max units dcm_rst_pw_min minimum duration of a rst pulse width 3 ?clkin cycles
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 49 dna port timing ta bl e 4 3 : dna_port interface timing symbol description min max units t dnassu setup time on shift before the rising edge of clk 1.0 ?ns t dnash hold time on shift after the rising edge of clk 0.5 ?ns t dnadsu setup time on din before the rising edge of clk 1.0 ?ns t dnadh hold time on din after the rising edge of clk 0.5 ?ns t dnarsu setup time on read before the rising edge of clk 5.0 10,000 ns t dnarh hold time on read after the rising edge of clk 0.0 ?ns t dnadcko clock-to-output delay on dout after rising edge of clk 0.5 1.5 ns t dnaclkf clk frequency 0.0 100 mhz t dnaclkh clk high time 1.0 ns t dnaclkl clk low time 1.0 ns notes: 1. the minimum read pulse width is 5 ns, and the maximum read pulse width is 10 s.
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 50 suspend mode timing x-ref target - figure 9 figure 9: suspend mode timing ta bl e 4 4 : suspend mode timing parameters symbol description min typ max units entering suspend mode t suspendhigh_awake rising edge of sus pend pin to falling edge of aw ake pin without glitch filter ( suspend_filter:no ) ?7 ?ns t suspendfilter adjustment to suspend pin rising e dge parameters when glitch filter enabled ( suspend_filter:yes ) +160 +300 +600 ns t suspend_gts rising edge of suspend pin until fpga output pins drive their defined suspend constraint behavior ?10 ?ns t suspend_gwe rising edge of suspend pin to write-protect lock on all writable clocked elements ?<5 ?ns t suspend_disable rising edge of the suspend pin to fpga input pins and interconnect disabled ? 340 ?ns exiting suspend mode t suspendlow_awake falling edge of the suspend pin to rising edge of the awake pin. does not include dcm lock time. ? 4 to 108 ? s t suspend_enable falling edge of the suspend pin to fpga input pins and interconnect re-enabled ? 3.7 to 109 ? s t awake_gwe1 rising edge of the awake pin until write-pr otect lock released on all writable clocked elements, using sw_clk:internalclock and sw_gwe_cycle:1 . ?67 ?ns t awake_gwe512 rising edge of the awake pin until write-pr otect lock released on all writable clocked elements, using sw_clk:internalclock and sw_gwe_cycle:512 . ?14 ?s t awake_gts1 rising edge of the awake pin until outputs return to the behavior described in the fpga application, using sw_clk:internalclock and sw_gts_cycle:1 . ?57 ?ns t awake_gts512 rising edge of the awake pin until outputs return to the behavior described in the fpga application, using sw_clk:internalclock and sw_gts_cycle:512 . ?14 ?s notes: 1. these parameters based on characterization. 2. for information on using the spartan-3a dsp suspend feature, see xapp480 : using suspend mode in spartan-3 generation fpgas . ds610-3_08_061207 blocked t suspend_disable t suspend_gwe t suspendhigh_awake t awake_gwe t awake_gts t suspend_gts suspend input awake output flip-flops, block ram, distributed ram fpga outputs fpga inputs, interconnect write protected defined by suspend constraint entering suspend mode exiting suspend mode sw_gts_cycle sw_gwe_cycle t suspend_enable t suspendlow_awake
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 51 configuration and jtag timing general configuration power-on/reconfigure timing x-ref target - figure 10 figure 10: waveforms for power-on and the beginning of configuration ta bl e 4 5 : power-on timing and the beginning of configuration symbol description device all speed grades units min max t por (2) the time from the application of v ccint , v ccaux , and v cco bank 2 supply voltage ramps (whichever occurs last) to the rising transition of the init_b pin all ?18ms t prog the width of the low-going pulse on the prog_b pin all 0.5 ?s t pl (2) the time from the rising edge of the prog_b pin to the rising transition on the init_b pin all ?2ms t init minimum low pulse width on init_b output all 300 ?ns t icck (3) the time from the rising edge of the init_b pin to the generation of the configuration clock signal at the cclk output pin all 0.5 4 s notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 7 . this means power must be applied to all v ccint , v cco , and v ccaux lines. 2. power-on reset and the clearing of configuration memory occurs during this period. 3. this specification applies only to the master serial, spi, and bpi modes. 4. for details on configuration, see ug332 spartan-3 generation configuration user guide . v ccint (supply) (supply) (supply) v ccaux v cco bank 2 prog_b (output) (open-drain) (input) init_b cclk ds529-3_01_052708 1.2v 2.5v t icck t prog t pl t por 1.0v 2.0v 2.0v 3.3v or 2.5v 3.3v or notes: 1. the v ccint , v ccaux , and v cco supplies can be applied in any order. 2. the low-going pulse on prog_b is optional after power-on but necessary for reconfiguration without a power cycle. 3. the rising edge of init_b samples the voltage levels applied to the mode pins (m0 - m2).
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 52 configuration clock (cclk) characteristics ta bl e 4 6 : master mode cclk output period by configrate option setting symbol description configrate setting (1) temperature range minimum maximum units t cclk1 cclk clock period by configrate setting 1 (power-on value) commercial 1,254 2,500 ns industrial 1,180 ns t cclk3 3 commercial 413 833 ns industrial 390 ns t cclk6 6 (default) commercial 207 417 ns industrial 195 ns t cclk7 7 commercial 178 357 ns industrial 168 ns t cclk8 8 commercial 156 313 ns industrial 147 ns t cclk10 10 commercial 123 250 ns industrial 116 ns t cclk12 12 commercial 103 208 ns industrial 97 ns t cclk13 13 commercial 93 192 ns industrial 88 ns t cclk17 17 commercial 72 147 ns industrial 68 ns t cclk22 22 commercial 54 114 ns industrial 51 ns t cclk25 25 commercial 47 100 ns industrial 45 ns t cclk27 27 commercial 44 93 ns industrial 42 ns t cclk33 33 commercial 36 76 ns industrial 34 ns t cclk44 44 commercial 26 57 ns industrial 25 ns t cclk50 50 commercial 22 50 ns industrial 21 ns t cclk100 100 commercial 11.2 25 ns industrial 10.6 ns notes: 1. set the configrate option value when generating a configuration bitstream.
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 53 ta bl e 4 7 : master mode cclk output frequency by configrate option setting symbol description configrate setting temperature range minimum maximum units f cclk1 equivalent cclk clock frequency by configrate setting 1 (power-on value) commercial 0.400 0.797 mhz industrial 0.847 mhz f cclk3 3 commercial 1.20 2.42 mhz industrial 2.57 mhz f cclk6 6 (default) commercial 2.40 4.83 mhz industrial 5.13 mhz f cclk7 7 commercial 2.80 5.61 mhz industrial 5.96 mhz f cclk8 8 commercial 3.20 6.41 mhz industrial 6.81 mhz f cclk10 10 commercial 4.00 8.12 mhz industrial 8.63 mhz f cclk12 12 commercial 4.80 9.70 mhz industrial 10.31 mhz f cclk13 13 commercial 5.20 10.69 mhz industrial 11.37 mhz f cclk17 17 commercial 6.80 13.74 mhz industrial 14.61 mhz f cclk22 22 commercial 8.80 18.44 mhz industrial 19.61 mhz f cclk25 25 commercial 10.00 20.90 mhz industrial 22.23 mhz f cclk27 27 commercial 10.80 22.39 mhz industrial 23.81 mhz f cclk33 33 commercial 13.20 27.48 mhz industrial 29.23 mhz f cclk44 44 commercial 17.60 37.60 mhz industrial 40.00 mhz f cclk50 50 commercial 20.00 44.80 mhz industrial 47.66 mhz f cclk100 100 commercial 40.00 88.68 mhz industrial 94.34 mhz ta bl e 4 8 : master mode cclk output minimum low and high time symbol description configrate setting units 1 3 6 7 8 10121317222527334450100 t mccl, t mcch master mode cclk minimum low and high time commercial 595 196 98.3 84.5 74.1 58.4 48.9 44. 1 34.2 25.6 22.3 20.9 17.1 12.3 10.4 5.3 ns industrial 560 185 92.6 79.8 69.8 55.0 46.0 41. 8 32.3 24.2 21.4 20.0 16.2 11.9 10.0 5.0 ns ta bl e 4 9 : slave mode cclk input low and high time symbol description min max units t sccl t scch cclk low and high time 5 ns
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 54 master serial and slave serial mode timing x-ref target - figure 11 figure 11: waveforms for master serial and slave serial configuration ta bl e 5 0 : timing for the master serial and slave serial configuration modes symbol description slave/ master all speed grades units min max clock-to-output times t cco the time from the falling transition on the cclk pin to data appearing at the dout pin both 1.5 10 ns setup times t dcc the time from the setup of data at the din pin to the rising transition at the cclk pin both 7 ?ns hold times t ccd the time from the rising transition at the cclk pin to the point when data is last held at the din pin master 0.0 ?ns slave 1.0 ?ns clock timing t cch high pulse width at the cclk input pin master see ta b l e 4 8 slave see ta b l e 4 9 t ccl low pulse width at the cclk input pin master see ta b l e 4 8 slave see ta b l e 4 9 f ccser frequency of the clock signal at the cclk input pin (2) no bitstream compression slave 0 100 mhz with bitstream compression 0 100 mhz notes: 1. the numbers in this table are based on the operating conditions set forth in ta b l e 7 . 2. for serial configuration with a daisy-chain of multiple fpgas, the maximum limit is 25 mhz. ds312-3_05_103105 bit 0 bit 1 bit n bit n+1 bit n-64 bit n-63 1/f ccser t sccl t dcc t ccd t scch t cco prog_b (input) din (input) dout (output) (open-drain) init_b (input/output) cclk t mccl t mcch
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 55 slave parallel mode timing x-ref target - figure 12 figure 12: waveforms for slave parallel configuration ta bl e 5 1 : timing for the slave parallel configuration mode symbol description all speed grades units min max setup times t smdcc (2) the time from the setup of data at the d0-d7 pi ns to the rising transition at the cclk pin 7 ?ns t smcscc setup time on the csi_b pin before the rising transition at the cclk pin 7 ?ns t smccw setup time on the rdwr_b pin before the rising transition at the cclk pin 17 ?ns hold times t smccd the time from the rising transition at the ccl k pin to the point when data is last held at the d0-d7 pins 1 ?ns t smcccs the time from the rising transition at the cclk pin to the point when a logic level is last held at the cso_b pin 0 ?ns t smwcc the time from the rising transition at the cclk pin to the point when a logic level is last held at the rdwr_b pin 0 ?ns clock timing t cch the high pulse width at the cclk input pin 5 ?ns t ccl the low pulse width at the cclk input pin 5 ?ns f ccpar frequency of the clock signal at the cclk input pin no bitstream compression 0 80 mhz with bitstream compression 0 80 mhz notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 7 . 2. some xilinx documents refer to parallel modes as ?selectmap? modes. d s 529- 3 _02_051607 byte 0 byte 1 byte n byte n+1 t s mwcc 1/f ccpar t s mccc s t s cch t s mccw t s mccd t s mc s cc t s mdcc prog_b (inp u t) (open-dr a in) init_b (inp u t) c s i_b rdwr_b (inp u t) (inp u t) cclk (inp u t s ) d0 - d7 t mcch t s ccl t mccl notes: 1. it is possible to abort configuration by pulling csi_b low in a given cclk cycle, then switching rdwr_b low or high in any su bsequent cycle for which csi_b remains low. the rdwr_b pin asynchronously controls the driver impedance of the d0?d7 bus. when rdwr_b switches high, be careful to avoid contention on the d0?d7 bus. 2. to pause configuration, pause cclk instead of de-asserting csi_b. see ug332, chapter 7, section ?non-continuous selectmap data loading? for more details.
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 56 serial peripheral interface (spi) configuration timing x-ref target - figure 13 figure 13: waveforms for serial peripheral interface (spi) configuration ta bl e 5 2 : timing for serial peripheral interface (spi) configuration mode symbol description minimum maximum units t cclk1 initial cclk clock period see ta bl e 4 6 t cclk n cclk clock period after fpga loads configrate setting see ta bl e 4 6 t minit setup time on vs[2:0] variant-select pins and m[2:0] mode pins before the rising edge of init_b 50 ?ns t initm hold time on vs[2:0] variant-select pins and m[2:0] m ode pins after the rising edge of init_b 0 ?ns t cco mosi output valid delay after cclk falling edge see ta bl e 5 0 t dcc setup time on din data input before cclk rising edge see ta bl e 5 0 t ccd hold time on din data input after cclk rising edge see ta bl e 5 0 t dh t dsu command (msb) t v t css <1:1:1> init_b m[2:0] t minit t initm din cclk (input) t cclk n t cclk1 vs[2:0] (input) new configrate active mode input pins m[2:0] and variant select input pins vs[2:0] are sampled when init_b goes high. after this point, input values do not matter until done goes high, at which point these pins become user-i/o pins. <0:0:1> pin initially pulled high by internal pull-up resistor if pudc_b input is low. pin initially high-impedance (hi-z) if pudc_b input is high. external pull-up resistor required on cso_b. t cclk1 t mccl n t mcch n (input) data data data data cso_b mosi t cco t mccl1 t mcch1 t dcc t ccd (input) prog_b pudc_b (input) pudc_b must be stable before init_b goes high and constant throughout the configuration process. ds529-3_06_102506 (open-drain) shaded values indicate specifications on attached spi flash prom. command (msb-1)
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 57 ta bl e 5 3 : configuration timing requirements for attached spi serial flash symbol description requirement units t ccs spi serial flash prom chip-select time ns t dsu spi serial flash prom data input setup time ns t dh spi serial flash prom data input hold time ns t v spi serial flash prom data clock-to-output time ns f c or f r maximum spi serial flash prom clock frequency (also depends on specific read command used) mhz notes: 1. these requirements are for successful fpga configuration in spi mode, where the fpga generates the cclk signal. the post-configuration timing can be different to support the specific needs of the application loaded into the fpga. 2. subtract additional printed circuit board routing delay as required by the application. t ccs t mccl 1 t cco ? t dsu t mccl 1 t cco ? t dh t mcch 1 t v t mccln t dcc ? f c 1 t cclkn min () ---------------------------------
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 58 byte peripheral interface (bpi) configuration timing x-ref target - figure 14 figure 14: waveforms for byte-wide periphera l interface (bpi) configuration ta bl e 5 4 : timing for byte-wide peripheral interface (bpi) configuration mode symbol description minimum maximum units t cclk1 initial cclk clock period see ta b l e 4 6 t cclk n cclk clock period after fpga loads configrate setting see ta b l e 4 6 t minit setup time on m[2:0] mode pins be fore the rising edge of init_b 50 ?ns t initm hold time on m[2:0] mode pins after the rising edge of init_b 0 ?ns t initaddr minimum period of initial a[25:0] address cycle; ldc[ 2:0] and hdc are asserted and valid 55t cclk1 cycles t cco address a[25:0] outputs valid after cclk falling edge see ta b l e 5 0 t dcc setup time on d[7:0] data inputs before cclk rising edge see t smdcc in ta b l e 5 1 t ccd hold time on d[7:0] data inputs after cclk rising edge 0 ?ns (inp u t) pudc_b m us t b e s t ab le b efore init_b goe s high a nd con s t a nt thro u gho u t the config u r a tion proce ss . d a t a d a t a d a t a addre ss addre ss d a t a addre ss byte 0 000_0000 init_b <0:1:0> m[2:0] t minit t initm ldc[2:0] hdc c s o_b byte 1 000_0001 cclk a[25:0] d[7:0] t dcc t ccd t avqv t cclk1 (inp u t) t initaddr t cclk n t cclk1 t cco pudc_b new configr a te a ctive pin initi a lly p u lled high b y intern a l p u ll- u p re s i s tor if pudc_b inp u t i s low. pin initi a lly high-imped a nce (hi-z) if pudc_b inp u t i s high. mode inp u t pin s m[2:0] a re sa mpled when init_b goe s high. after thi s point, inp u t v a l u e s do not m a tter u ntil done goe s high, a t which point the mode pin s b ecome us er-i/o pin s . (inp u t) prog_b (inp u t) d s 529- 3 _05_090610 (open-dr a in) s h a ded v a l u e s indic a te s pecific a tion s on a tt a ched p a r a llel nor fl as h prom.
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 59 ta bl e 5 5 : configuration timing requirements fo r attached parallel nor bpi flash symbol description requirement units t ce (t elqv ) parallel nor flash prom chip-select time ns t oe (t glqv ) parallel nor flash prom output-enable time ns t acc (t avqv ) parallel nor flash prom read access time ns t byte (t flqv, t fhqv ) for x8/x16 proms only: byte# to output valid time (3) ns notes: 1. these requirements are for successful fpga configuration in bpi mode, where the fpga generates the cclk signal. the post-configuration timing can be different to support the specific needs of the application loaded into the fpga. 2. subtract additional printed circuit board routing delay as required by the application. 3. the initial byte# timing can be extended using an external, appr opriately sized pull-down resistor on the fpga?s ldc2 pin. th e resistor value also depends on whether the fpga?s pudc_b pin is high or low. t ce t initaddr t oe t initaddr t acc 50% t cclkn min () t cco t dcc pcb ? ? ? t byte t initaddr
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 60 ieee 1149.1/1532 jtag test access port timing x-ref target - figure 15 figure 15: jtag waveforms ta bl e 5 6 : timing for the jtag (2) test access port symbol description all speed grades units min max clock-to-output times t tcktdo the time from the falling transition on the tck pin to data appearing at the tdo pin 1.0 11.0 ns setup times t tditck the time from the se tup of data at the tdi pin to the rising transition at the tck pin all functions except those shown below 7.0 ?ns boundary scan commands (intest, extest, sample) 13.0 t tmstck the time from the setup of a logic level at the tm s pin to the rising transition at the tck pin 7.0 ?ns hold times t tcktdi the time from the rising transition at the tck pin to the point when data is last held at the tdi pin all functions except those shown below 0 ?ns configuration commands (cfg_in, isc_program) 3.5 t tcktms the time from the rising transition at the tck pin to the point when a logic level is last held at the tms pin 0 ?ns clock timing t cch the high pulse width at the tck pin a ll functions except isc_dna command 5 ?ns t ccl the low pulse width at the tck pin 5 ?ns t cchdna the high pulse width at the tck pi n during isc_dna command 10 10,000 ns t ccldna the low pulse width at the tck pin 10 10,000 ns f tck frequency of the tck signal bypass or highz instructions 0 33 mhz all operations except for byp ass or highz instructions 20 notes: 1. the numbers in this table are based on the operating conditions set forth in ta b l e 7 . 2. for details on jtag, see chapter 9, ?jtag configuraton mode and boundary-scan? in ug332 : spartan-3 generation configuration user guide . tck t tm s tck tm s tdi tdo (inp u t) (inp u t) (inp u t) (o u tp u t) t tcktm s t tcktdi t tcktdo t tditck d s 099_06_090610 t cch t ccl 1/f tck
spartan-3a dsp fpga family: dc and switching characteristics ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 61 revision history the following table shows the revision history for this document. date version revision 04/02/07 1.0 initial xilinx release. 05/25/07 1.0.1 minor edits. 06/18/07 1.2 updated for v1.29 production speed files. noted banking rules in ta bl e 1 1 and ta bl e 1 2 . added diff_hstl_i and diff_hstl_iii to ta b l e 1 2 , ta b l e 1 3 , and ta b l e 2 6 . updated tmds dc characteristics in ta bl e 1 3 . updated i/o test method values in ta bl e 2 6 . added simultaneously switching output limits in ta bl e 2 8 . updated dsp48a timing symbols, descriptions, and values in ta b l e 3 4 . added power-on timing in ta bl e 4 5 . added cclk specifications for commercial in ta b l e 4 6 through ta b l e 4 8 . updated slave parallel timing in ta b l e 5 1 . updated jtag specifications in ta b l e 5 6 . 07/16/07 2.0 added low-power options and updated typical values for quiescent current in ta b l e 9 . updated dsp48a timing in ta b l e 3 4 and ta b l e 3 5 . 06/02/08 2.1 improved v ccauxt and v cco2t por minimum in ta b l e 4 and updated v cco por levels in figure 10 . added v in to recommended operating conditions in ta b l e 7 and added reference to xapp459 , ?eliminating i/o coupling effects when interfacing large-swing single-ended signals to user i/o pins.? reduced typical i ccintq and i ccauxq quiescent current values by 20%-44% in ta bl e 9 . increased v il max to 0.4v for lvcmos12/15/18 and improved v ih min to 0.7v for lvcmos12 in ta b l e 1 0 . changed v ol max to 0.4v and v oh min to v cco ?0.4v for lvcmos15/18 in ta b l e 1 1 . added reference to v ccaux in simultaneously switching output guidelines . removed dna_retention limit of 10 years in ta bl e 1 4 since number of read cycles is the only unique limit. updated speed files to v1.31 in ta b l e 1 6 and elsewhere. updated iob setup and hold times with device-specific values in ta bl e 1 9 . added reference to sample window in ta bl e 2 0 . updated iob propagation times with device-specific values in ta bl e 2 1 . improved sstl_18_ii sso value in ta bl e 2 8 . improved f bufg for -4 to 334 mhz in ta b l e 3 2 . added references to 375 mhz performance via scd 4103 in ta b l e 3 2 , ta bl e 3 7 , ta b l e 3 8 , and ta bl e 3 9 . added explanatory footnotes to dsp48a timing tables. simplified dsp48a f max to value with all registers used in ta bl e 3 5 . improved fbufg in ta bl e 3 2 for -4 speed grade. updated cclk output maximum period in ta b l e 4 6 to match minimum frequency in ta bl e 4 7 . replaced bpi with spi specification descriptions in ta b l e 5 2 . corrected bpi figure 14 and ta bl e 5 4 from falling edge to rising edge. added references to spart an-3 generation user guides. updated links. 03/11/09 2.2 changed typical quiescent current temperature from ambient to quiescent. updated selected i/o standard dc characteristics. removed pcix iostandard due to limited pcix interface support. added t iopi and t iopid to ta bl e 2 1 . updated bpi configuration waveforms in figure 14 and updated ta bl e 5 5 . removed references to scd 4103. 10/04/10 3.0 added i ik to ta bl e 3 . updated description for v in in ta b l e 7 including adding note 4. also, added note 2 to i l in ta bl e 8 to note potential leakage between pins of a differential pair. added note 6 to ta b l e 1 0 . updated notes 5 and 6 in ta b l e 1 2 . corrected symbols for t suspend_gts and t suspend_gwe in ta b l e 4 4 .
ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 62 ? copyright 2007?2010 xilinx, inc. xilinx, the xilinx logo, virt ex, spartan, ise, and other designated brands included herein a re trademarks of xilinx in the united states and other countries. pci and pci-x are trademarks of pci-sig and used under license. all other trademarks are the property of their respective owners. introduction this section describes how the various pins on a spartan?-3a dsp fpga connect within the supported component packages and provides device-specific thermal characteristics. for general information on the pin functions and the package characteristics, see the packaging section in ug331 : spartan-3 generation fpga user guide. spartan-3a dsp fpgas are available in both standard and pb-free, rohs versions of each package, with the pb-free version adding a ?g? to the middle of the package code. exce pt for the thermal characteristics, all information for the standard package applies equally to the pb-free package. pin types most pins on a spartan-3a dsp fpga are general-purpose, user-defined i/o pins. there are, however, up to 12 different functional types of pins on spartan-3a dsp packages, as outlined in ta b l e 5 7 . in the package footprint drawings that follow, the individual pins are color-coded according to pin type as in the table. 101 spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 product specification ta bl e 5 7 : types of pins on spartan-3a dsp fpgas type/color code description pin name(s) in type i/o unrestricted, general-purpose user-i/o pin. most pins can be paired together to form differential i/os. io_# io_lxxy_# input unrestricted, general-purpose input-only pin. this pin does not have an output structure, differential termination resistor, or pci clamp diode. ip_# ip_lxxy_# dual dual-purpose pin used in some configurati on modes during the configuration process and then usually available as a user i/o after c onfiguration. if the pin is not used during configuration, this pin behaves as an i/o-type pin. see ug332 : spartan-3 generation configuration user guide for additional information on these signals. m[2:0] pudc_b cclk mosi/csi_b d[7:1] d0/din cso_b rdwr_b init_b a[25:0] vs[2:0] ldc[2:0] hdc vref dual-purpose pin that is either a user-i/o pin or input-only pin, or, al ong with all other vref pins in the same bank, provides a reference volt age input for certain i/o standards. if used for a reference voltage within a bank, all vref pins within the bank must be connected. ip/vref_# ip_lxxy_#/vref_# io/vref_# io_lxxy_#/vref_# clk either a user-i/o pin or an input to a specific clock buffer driver. packages have 16 global clock inputs that optionally clock the entire device. the rhclk inputs optionally clock the right half of the device. the lhclk inputs optionally clock the left half of the device. see the using global clock resources chapter in ug331 : spartan-3 generation fpga user guide for additional information on these signals. io_lxxy_#/gclk[15:0], io_lxxy_#/lhclk[7:0], io_lxxy_#/rhclk[7:0] config dedicated configuration pin, two per device. no t available as a user-i/o pin. every package has two dedicated configuration pins. these pins are powered by vccaux. see the ug332 : spartan-3 generation configuration user guide for additional information on the done and prog_b signals. done, prog_b
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 63 package pins by type each package has three separate voltage supply inputs?vccint, vccaux, and vcco?and a common ground return, gnd. the numbers of pins dedicated to these functions vary by package, as shown in ta b l e 5 8 . a majority of package pins are user-defined i/o or input pins. however, the numbers and characteristics of these i/o depend on the device type and the package in which it is available, as shown in ta bl e 5 9 . the table shows the maximum number of single-ended i/o pins available, assuming that all i/o- , input -, dual -, vref -, and clk -type pins are used as g eneral-purpose i/o. awake is counted here as a dual-purpose i/o pin. likewise, the table shows the maximum number of differential pin-pairs available on the package. finally, the table shows how the total maximum user-i/os are distributed by pin type, including the number of unconnected?n.c.?pins on the device. not all i/o standards are supported on all i/o banks. the left and right banks (i/o banks 1 and 3) support higher output drive current than the top and bottom banks (i/o banks 0 and 2). similarly, true differential output standards, such as lvds, rsds, ppds, minilvds, and tmds, are only supported in the top or bottom banks (i/o banks 0 and 2). inputs are unrestricted. for more details, see the using i/o resources chapter in ug331 . pwr mgmt control and status pins for the power-savin g suspend mode. suspend is a dedicated pin and is powered by vccaux. awake is a dual-p urpose pin. unless suspend mode is enabled in the application, awake is available as a user-i/o pin. suspend, awake jtag dedicated jtag pin - 4 per device. not available as a user-i/o pin. every package has four dedicated jtag pins. these pins are powered by vccaux. tdi, tms, tck, tdo gnd dedicated ground pin. the number of gnd pins depends on the package used. all must be connected. gnd vccaux dedicated auxiliary power supply pin. the number of vccaux pins depends on the package used. all must be connected. set on b oard and using config vccaux constraint. vccaux vccint dedicated internal core logic power supply pi n. the number of vccint pins depends on the package used. all must be connected to +1.2v. vccint vcco along with all the other vcco pi ns in the same bank, this pin supplies power to the output buffers within the i/o bank and sets the input threshold voltage for some i/o standards. all must be connected. vcco_# n.c. this package pin is not connected in this sp ecific device/package combination but may be connected in larger devices in the same package. n.c. notes: 1. # = i/o bank number, an integer between 0 and 3. ta bl e 5 7 : types of pins on spartan-3a dsp fpgas (cont?d) type/color code description pin name(s) in type ta bl e 5 8 : power and ground supply pins by package package device vccint vccaux vcco gnd cs484 xc3sd1800a 36 24 24 84 xc3sd3400a 36 24 24 84 fg676 xc3sd1800a 23 14 36 77 xc3sd3400a 36 24 40 100 ta bl e 5 9 : maximum user i/o by package package device maximum user i/os and input-only maximum input-only maximum differential pairs all possible i/os by type i/o input dual vref (1) clk n.c. cs484 xc3sd1800a 309 60 140 156 41 52 28 32 0 xc3sd3400a 309 60 140 156 41 52 28 32 0 fg676 xc3sd1800a 519 110 227 314 82 52 39 32 0 xc3sd3400a 469 60 213 314 34 52 37 32 0 notes: 1. some vrefs are on input pins. see pinout tables for details.
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 64 electronic versions of the package pinout tables and foot- prints are available fo r download from the xilinx? website. using a spreadsheet program, the data can be sorted and reformatted according to any specific needs. similarly, the ascii-text file is easily parsed by most scripting programs. www.xilinx.com/support/document ation/data_sheets/s3a_pin.zip package overview ta bl e 6 0 shows the two low-cost, space-saving production package styles for the spartan-3a dsp family. each package style is available as a standard and an environmentally friendly lead-free (pb-free) option. the pb-free packages include an extra ?g? in the package style name. for example, the standard ?cs484? package becomes ?csg484? when ordered as the pb-free option. the mechanical dimensions of the standard and pb-free packages are similar, as shown in the mechanical drawings provided in ta b l e 6 1 . for additional package information, see ug112 : device package user guide . mechanical drawings detailed mechanical drawings for each package type are available from the xilinx we b site at the specified location in ta bl e 6 1 . material declaration data sheets (mdds) are also available on the xilinx web site for each package. ta bl e 6 0 : spartan-3a dsp family package options package leads type maximum i/o lead pitch (mm) footprint area (mm) height (mm) mass (1) (g) cs484 / csg484 484 chip-scale ball grid array (cs) 309 0.8 19 x 19 1.80 1.4 fg676 / fgg676 676 fine-pitch ball grid array (fbga) 519 1.0 27 x 27 2.60 3.4 notes: 1. package mass is 10%. ta bl e 6 1 : xilinx package documentation package drawing mdds cs484 package drawing pk230_cs484 csg484 pk231_csg484 fg676 package drawing pk155_fg676 fgg676 pk111_fgg676
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 65 package thermal characteristics the power dissipated by an fpga application has implications on package selection and system design. the power consumed by a spartan-3a dsp fpga is reported using either the xpower power estimator or the xpower analyzer calculator integrated in the xilinx ise? development software. ta bl e 6 2 provides the thermal characteristics for the various spartan-3a dsp device package offerings. this information is also available using the thermal query tool . the junction-to-case thermal resistance ( jc ) indicates the difference between the temperature measured on the package body (case) and the die junction temperature per wa tt of power consumption. the junction-to-board ( jb ) value similarly reports the difference between the board and junction temperature. the junction-to-ambient ( ja ) value reports the temperature difference between the ambient environment and the junction temperature. the ja value is reported at different air velocities, measured in linear feet per minute (lfm). the ?still air (0 lfm)? column shows the ja value in a system without a fan. the thermal resistance drops with increasing air flow. ta bl e 6 2 : spartan-3a dsp fpga package thermal characteristics package device junction-to-case ( jc ) junction-to- board ( jb ) junction-to-ambient ( ja ) at different air flows units still air (0 lfm) 250 lfm 500 lfm 750 lfm cs484 csg484 xc3sd1800a 4.1 6.8 18.0 13.3 12.3 11.5 c/w xc3sd3400a 3.5 5.6 16.9 12.2 11.0 10.4 c/w fg676 fgg676 xc3sd1800a 4.7 7.8 15.9 11.6 10.6 10.0 c/w xc3sd3400a 3.8 6.4 14.7 10.5 9.4 8.9 c/w
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 66 cs484: 484-ball chip-sca le ball grid array the 484-ball chip-scale ball grid array, cs484, supports both the xc3sd1800a and xc3sd3400a fpgas. there are no pinout differences between the two devices. ta bl e 6 3 lists all the cs484 package pins. they are sorted by bank number and then by pin name. pairs of pins that form a differential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. an electronic version of this package pinout table and footprint diagram is available for download from the xilinx website at www.xilinx.com/support/documentat ion/data_sheets/s3a_pin.zip pinout table ta bl e 6 3 : spartan-3a dsp cs484 pinout bank pin name cs484 ball type 0 io_l30n_0 a3 i/o 0 io_l28n_0 a4 i/o 0 io_l25n_0 a5 i/o 0 io_l25p_0 a6 i/o 0 io_l24n_0/vref_0 a7 vref 0 io_l20p_0/gclk10 a8 gclk 0 io_l18p_0/gclk6 a9 gclk 0 ip_0 a10 input 0 io_l15n_0 a11 i/o 0 ip_0 a12 input 0 io_l11p_0 a13 i/o 0 io_l10p_0 a14 i/o 0 ip_0 a15 input 0 io_l06p_0/vref_0 a16 vref 0 io_l06n_0 a17 i/o 0 ip_0 a18 input 0 io_l07n_0 a19 i/o 0 io_0 a20 i/o 0 io_l30p_0 b3 i/o 0 io_l28p_0 b4 i/o 0 io_l24p_0 b6 i/o 0 io_l20n_0/gclk11 b8 gclk 0 io_l18n_0/gclk7 b9 gclk 0 io_l15p_0 b11 i/o 0 io_l11n_0 b13 i/o 0 io_l10n_0 b15 i/o 0 io_l03p_0 b17 i/o 0 io_l02n_0 b19 i/o 0 io_l07p_0 b20 i/o 0 io_l29n_0 c4 i/o 0 ip_0 c5 input 0 io_l21p_0 c6 i/o 0 io_l26p_0 c7 i/o 0 io_l22p_0 c8 i/o 0 io_l16p_0 c9 i/o 0 ip_0 c10 input 0 ip_0/vref_0 c11 vref 0 io_l14n_0 c12 i/o 0 io_l14p_0 c13 i/o 0 ip_0 c14 input 0 io_l12n_0/vref_0 c15 vref 0 io_l08n_0 c16 i/o 0 io_l03n_0 c17 i/o 0 io_l02p_0/vref_0 c18 vref 0 io_l01n_0 c19 i/o 0 io_l29p_0 d5 i/o 0 io_l21n_0 d6 i/o 0 io_l26n_0 d7 i/o 0 io_l22n_0 d9 i/o 0 io_l16n_0 d10 i/o 0 io_l09n_0 d13 i/o 0 io_l12p_0 d14 i/o 0 io_l08p_0 d15 i/o 0 ip_0 d17 input 0 ip_0 d18 input 0 io_l01p_0 d19 i/o 0 ip_0 e6 input 0 io_l31p_0/vref_0 e7 vref 0 io_l27n_0 e8 i/o 0 ip_0 e10 input 0 io_l19n_0/gclk9 e11 gclk 0 io_l17p_0/gclk4 e12 gclk 0 io_l09p_0 e13 i/o 0 io_l05p_0 e15 i/o 0 io_l04p_0 e16 i/o 0 ip_0 e17 input 0 io_l31n_0/pudc_b f7 dual 0 io_l27p_0 f8 i/o 0 io_l23n_0 f9 i/o ta b l e 6 3 : spartan-3a dsp cs484 pinout (cont?d) bank pin name cs484 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 67 0 io_l19p_0/gclk8 f10 gclk 0 io_l17n_0/gclk5 f11 gclk 0 ip_0 f12 input 0 io_l13n_0 f13 i/o 0 io_l13p_0 f14 i/o 0 io_l05n_0 f15 i/o 0 io_l04n_0 f16 i/o 0 io_l23p_0 g8 i/o 0 vcco_0 b5 vcco 0 vcco_0 b10 vcco 0 vcco_0 b14 vcco 0 vcco_0 b18 vcco 0 vcco_0 e9 vcco 0 vcco_0 e14 vcco 1 io_l02n_1/ldc0 aa22 dual 1 ip_l39n_1 c21 input 1 ip_l39p_1/vref_1 c22 vref 1 io_l36p_1/a20 d20 dual 1 io_l37p_1/a22 d21 dual 1 io_l37n_1/a23 d22 dual 1 io_l36n_1/a21 e19 dual 1 io_l35n_1 e20 i/o 1 io_l33n_1 e22 i/o 1 io_l38n_1/a25 f18 dual 1 io_l38p_1/a24 f19 dual 1 io_l30n_1/a19 f20 dual 1 io_l35p_1 f21 i/o 1 io_l33p_1 f22 i/o 1 io_l34p_1 g17 i/o 1 io_l34n_1 g18 i/o 1 io_l30p_1/a18 g19 dual 1 ip_l31n_1 g20 input 1 io_l28n_1 g22 i/o 1 io_l26p_1/a14 h17 dual 1 io_l26n_1/a15 h18 dual 1 io_l32n_1 h20 i/o 1 ip_l31p_1/vref_1 h21 vref 1 io_l28p_1 h22 i/o 1 io_l29n_1/a17 j17 dual 1 io_l32p_1 j19 i/o 1 io_l25n_1/a13 j20 dual 1 ip_l27p_1 j21 input ta bl e 6 3 : spartan-3a dsp cs484 pinout (cont?d) bank pin name cs484 ball type 1 ip_l27n_1 j22 input 1 io_l29p_1/a16 k16 dual 1 ip_l23n_1 k17 input 1 io_l24n_1 k18 i/o 1 io_l24p_1 k19 i/o 1 io_l25p_1/a12 k20 dual 1 io_l22n_1/a11 k22 dual 1 io_l21n_1/rhclk7 l17 rhclk 1 ip_l23p_1/vref_1 l18 vref 1 io_l20n_1/rhclk5 l20 rhclk 1 io_l20p_1/rhclk4 l21 rhclk 1 io_l22p_1/a10 l22 dual 1 io_l18n_1/rhclk1 m17 rhclk 1 io_l21p_1/irdy1/rhclk6 m18 rhclk 1 io_l19n_1/trdy1/rhclk3 m20 rhclk 1 io_l17n_1/a9 m22 dual 1 io_l13p_1/a2 n17 dual 1 io_l18p_1/rhclk0 n18 rhclk 1 io_l15n_1/a7 n19 dual 1 io_l15p_1/a6 n20 dual 1 io_l19p_1/rhclk2 n21 rhclk 1 io_l17p_1/a8 n22 dual 1 io_l13n_1/a3 p16 dual 1 ip_l12n_1/vref_1 p17 vref 1 io_l10p_1 p19 i/o 1 ip_l16n_1 p20 input 1 io_l14n_1/a5 p22 dual 1 ip_l12p_1 r17 input 1 io_l10n_1 r18 i/o 1 io_l07p_1 r19 i/o 1 io_l07n_1 r20 i/o 1 ip_l16p_1/vref_1 r21 vref 1 io_l14p_1/a4 r22 dual 1 io_l05n_1 t17 i/o 1 io_l05p_1 t18 i/o 1 io_l09n_1 t20 i/o 1 io_l11n_1/vref_1 t22 vref 1 io_l01p_1/hdc u18 dual 1 io_l01n_1/ldc2 u19 dual 1 io_l09p_1 u20 i/o 1 ip_l08n_1/vref_1 u21 vref 1 io_l11p_1 u22 i/o ta b l e 6 3 : spartan-3a dsp cs484 pinout (cont?d) bank pin name cs484 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 68 1 io_l03n_1/a1 v20 dual 1 ip_l08p_1 v22 input 1 io_l03p_1/a0 w19 dual 1 ip_l04n_1/vref_1 w20 vref 1 ip_l04p_1 w21 input 1 io_l06p_1 w22 i/o 1 io_l02p_1/ldc1 y21 dual 1 io_l06n_1 y22 i/o 1 vcco_1 e21 vcco 1 vcco_1 j18 vcco 1 vcco_1 k21 vcco 1 vcco_1 p18 vcco 1 vcco_1 p21 vcco 1 vcco_1 v21 vcco 2 io_l01p_2/m1 aa3 dual 2 io_l04n_2 aa4 i/o 2 ip_2 aa6 input 2 io_l08n_2 aa8 i/o 2 io_l12n_2/d6 aa10 dual 2 io_l16p_2/gclk14 aa12 gclk 2 io_l18n_2/gclk3 aa14 gclk 2 io_l19p_2 aa15 i/o 2 io_l22p_2/awake aa17 pwrmgmt 2 io_l27n_2 aa19 i/o 2 io_l30p_2 aa20 i/o 2 ip_2/vref_2 ab2 vref 2 io_l01n_2/m0 ab3 dual 2 io_l04p_2 ab4 i/o 2 io_l05p_2 ab5 i/o 2 io_l05n_2 ab6 i/o 2 io_l08p_2 ab7 i/o 2 io_l09p_2/vs1 ab8 dual 2 io_l09n_2/vs0 ab9 dual 2 io_l12p_2/d7 ab10 dual 2 ip_2/vref_2 ab11 vref 2 io_l16n_2/gclk15 ab12 gclk 2 io_l18p_2/gclk2 ab13 gclk 2 io_l19n_2 ab14 i/o 2 ip_2 ab15 input 2 io_l22n_2/dout ab16 dual 2 io_l23p_2 ab17 i/o 2 io_l23n_2 ab18 i/o ta bl e 6 3 : spartan-3a dsp cs484 pinout (cont?d) bank pin name cs484 ball type 2 io_l27p_2 ab19 i/o 2 io_l30n_2 ab20 i/o 2 io_l02n_2/cso_b u7 dual 2 io_l11n_2 u8 i/o 2 io_l10n_2 u9 i/o 2 io_l14n_2/d4 u10 dual 2 io_l17p_2/gclk0 u12 gclk 2 io_l20p_2 u13 i/o 2 io_l25p_2 u14 i/o 2 io_l25n_2 u15 i/o 2 io_l28p_2 u16 i/o 2 io_l02p_2/m2 v6 dual 2 io_l11p_2 v7 i/o 2 io_l06n_2 v8 i/o 2 io_l10p_2 v10 i/o 2 io_l14p_2/d5 v11 dual 2 io_l17n_2/gclk1 v12 gclk 2 io_l20n_2/mosi/csi_b v13 dual 2 ip_2/vref_2 v15 vref 2 io_l28n_2 v16 i/o 2 io_l31n_2/cclk v17 dual 2 ip_2/vref_2 w4 vref 2 io_l03p_2 w5 i/o 2 io_l07n_2/vs2 w6 dual 2 io_l06p_2 w8 i/o 2 ip_2/vref_2 w9 vref 2 ip_2 w10 input 2 ip_2/vref_2 w13 vref 2 io_l21n_2 w14 i/o 2 io_l24p_2/init_b w15 dual 2 io_l31p_2/d0/din/miso w17 dual 2 ip_2/vref_2 w18 vref 2 io_l03n_2 y4 i/o 2 io_l07p_2/rdwr_b y5 dual 2 ip_2 y6 input 2 ip_2 y7 input 2 io_l13p_2 y8 i/o 2 io_l13n_2 y9 i/o 2 io_l15n_2/gclk13 y10 gclk 2 io_l15p_2/gclk12 y11 gclk 2 ip_2 y12 input 2 io_l21p_2 y13 i/o ta b l e 6 3 : spartan-3a dsp cs484 pinout (cont?d) bank pin name cs484 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 69 2 ip_2/vref_2 y14 vref 2 io_l24n_2/d3 y15 dual 2 io_l29n_2 y16 i/o 2 io_l29p_2 y17 i/o 2 io_l26p_2/d2 y18 dual 2 io_l26n_2/d1 y19 dual 2 vcco_2 aa5 vcco 2 vcco_2 aa9 vcco 2 vcco_2 aa13 vcco 2 vcco_2 aa18 vcco 2 vcco_2 v9 vcco 2 vcco_2 v14 vcco 3 ip_l39n_3/vref_3 aa1 vref 3 io_l02n_3 c1 i/o 3 io_l02p_3 c2 i/o 3 ip_l04p_3 d1 input 3 ip_l08p_3 d3 input 3 ip_l08n_3 d4 input 3 ip_l04n_3/vref_3 e1 vref 3 io_l09p_3 e3 i/o 3 io_l09n_3 e4 i/o 3 io_l06n_3 f1 i/o 3 io_l06p_3 f2 i/o 3 io_l01p_3 f3 i/o 3 io_l03p_3 f4 i/o 3 io_l03n_3 f5 i/o 3 io_l11p_3 g1 i/o 3 io_l01n_3 g3 i/o 3 io_l07p_3 g5 i/o 3 io_l07n_3 g6 i/o 3 io_l11n_3 h1 i/o 3 io_l14p_3 h2 i/o 3 io_l05p_3 h3 i/o 3 io_l05n_3 h4 i/o 3 io_l10p_3 h5 i/o 3 io_l10n_3 h6 i/o 3 io_l14n_3/vref_3 j1 vref 3 ip_l16p_3 j3 input 3 ip_l16n_3 j4 input 3 ip_l12p_3 j6 input 3 ip_l12n_3/vref_3 j7 vref 3 io_l19p_3/lhclk2 k1 lhclk ta bl e 6 3 : spartan-3a dsp cs484 pinout (cont?d) bank pin name cs484 ball type 3 io_l17p_3 k2 i/o 3 io_l17n_3 k3 i/o 3 io_l13p_3 k4 i/o 3 io_l13n_3 k5 i/o 3 io_l15p_3 k6 i/o 3 io_l19n_3/irdy2/lhclk3 l1 lhclk 3 io_l20p_3/lhclk4 l3 lhclk 3 io_l15n_3 l5 i/o 3 io_l18p_3/lhclk0 l6 lhclk 3 io_l22p_3/vref_3 m1 vref 3 io_l20n_3/lhclk5 m2 lhclk 3 ip_l23p_3 m3 input 3 io_l18n_3/lhclk1 m5 lhclk 3 io_l21p_3/trdy2/lhclk6 m6 lhclk 3 io_l22n_3 n1 i/o 3 ip_l31p_3 n3 input 3 ip_l23n_3 n4 input 3 io_l24n_3 n5 i/o 3 io_l24p_3 n6 i/o 3 io_l21n_3/lhclk7 n7 lhclk 3 io_l25p_3 p1 i/o 3 io_l25n_3 p2 i/o 3 ip_l31n_3 p3 input 3 io_l32p_3/vref_3 p4 vref 3 io_l26p_3 p6 i/o 3 io_l28n_3 r1 i/o 3 io_l28p_3 r2 i/o 3 io_l34p_3 r3 i/o 3 io_l32n_3 r5 i/o 3 io_l26n_3 r6 i/o 3 io_l30p_3 t1 i/o 3 ip_l27p_3 t3 input 3 io_l34n_3 t4 i/o 3 io_l29n_3 t5 i/o 3 io_l29p_3 t6 i/o 3 io_l30n_3 u1 i/o 3 io_l33p_3 u2 i/o 3 ip_l27n_3 u3 input 3 io_l38p_3 u4 i/o 3 io_l38n_3 u5 i/o 3 io_l33n_3 v1 i/o 3 io_l36n_3 v3 i/o ta b l e 6 3 : spartan-3a dsp cs484 pinout (cont?d) bank pin name cs484 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 70 3 io_l36p_3 v4 i/o 3 io_l35n_3 w1 i/o 3 io_l37n_3 w2 i/o 3 io_l37p_3 w3 i/o 3 io_l35p_3 y1 i/o 3 ip_l39p_3 y2 input 3 vcco_3 e2 vcco 3 vcco_3 j2 vcco 3 vcco_3 j5 vcco 3 vcco_3 n2 vcco 3 vcco_3 p5 vcco 3 vcco_3 v2 vcco gnd gnd a1 gnd gnd gnd a22 gnd gnd gnd aa7 gnd gnd gnd aa11 gnd gnd gnd aa16 gnd gnd gnd ab1 gnd gnd gnd ab22 gnd gnd gnd b7 gnd gnd gnd b12 gnd gnd gnd b16 gnd gnd gnd c3 gnd gnd gnd c20 gnd gnd gnd d8 gnd gnd gnd d11 gnd gnd gnd d16 gnd gnd gnd f6 gnd gnd gnd f17 gnd gnd gnd g2 gnd gnd gnd g4 gnd gnd gnd g9 gnd gnd gnd g11 gnd gnd gnd g13 gnd gnd gnd g15 gnd gnd gnd g21 gnd gnd gnd h7 gnd gnd gnd h8 gnd gnd gnd h10 gnd gnd gnd h12 gnd gnd gnd h14 gnd gnd gnd h16 gnd ta bl e 6 3 : spartan-3a dsp cs484 pinout (cont?d) bank pin name cs484 ball type gnd gnd h19 gnd gnd gnd j9 gnd gnd gnd j11 gnd gnd gnd j13 gnd gnd gnd j15 gnd gnd gnd k8 gnd gnd gnd k10 gnd gnd gnd k12 gnd gnd gnd k14 gnd gnd gnd l2 gnd gnd gnd l7 gnd gnd gnd l9 gnd gnd gnd l11 gnd gnd gnd l13 gnd gnd gnd l15 gnd gnd gnd l19 gnd gnd gnd m4 gnd gnd gnd m8 gnd gnd gnd m10 gnd gnd gnd m12 gnd gnd gnd m14 gnd gnd gnd m16 gnd gnd gnd m21 gnd gnd gnd n9 gnd gnd gnd n11 gnd gnd gnd n13 gnd gnd gnd n15 gnd gnd gnd p8 gnd gnd gnd p10 gnd gnd gnd p12 gnd gnd gnd p14 gnd gnd gnd r4 gnd gnd gnd r7 gnd gnd gnd r9 gnd gnd gnd r11 gnd gnd gnd r13 gnd gnd gnd r15 gnd gnd gnd r16 gnd gnd gnd t2 gnd gnd gnd t8 gnd gnd gnd t10 gnd gnd gnd t12 gnd ta b l e 6 3 : spartan-3a dsp cs484 pinout (cont?d) bank pin name cs484 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 71 gnd gnd t14 gnd gnd gnd t15 gnd gnd gnd t19 gnd gnd gnd t21 gnd gnd gnd u6 gnd gnd gnd u11 gnd gnd gnd u17 gnd gnd gnd w7 gnd gnd gnd w12 gnd gnd gnd w16 gnd gnd gnd y3 gnd gnd gnd y20 gnd vccaux suspend v19 pwrmgmt vccaux prog_b a2 config vccaux done ab21 config vccaux tck a21 jtag vccaux tms b1 jtag vccaux tdo b22 jtag vccaux tdi d2 jtag vccaux vccaux aa2 vccaux vccaux vccaux aa21 vccaux vccaux vccaux b2 vccaux vccaux vccaux b21 vccaux vccaux vccaux d12 vccaux vccaux vccaux e5 vccaux vccaux vccaux e18 vccaux vccaux vccaux g10 vccaux vccaux vccaux g12 vccaux vccaux vccaux g14 vccaux vccaux vccaux j16 vccaux vccaux vccaux k7 vccaux vccaux vccaux l4 vccaux vccaux vccaux l16 vccaux vccaux vccaux m7 vccaux vccaux vccaux m19 vccaux vccaux vccaux n16 vccaux vccaux vccaux p7 vccaux vccaux vccaux t9 vccaux vccaux vccaux t11 vccaux vccaux vccaux t13 vccaux vccaux vccaux v5 vccaux vccaux vccaux v18 vccaux ta bl e 6 3 : spartan-3a dsp cs484 pinout (cont?d) bank pin name cs484 ball type vccaux vccaux w11 vccaux vccint vccint g7 vccint vccint vccint g16 vccint vccint vccint h9 vccint vccint vccint h11 vccint vccint vccint h13 vccint vccint vccint h15 vccint vccint vccint j8 vccint vccint vccint j10 vccint vccint vccint j12 vccint vccint vccint j14 vccint vccint vccint k9 vccint vccint vccint k11 vccint vccint vccint k13 vccint vccint vccint k15 vccint vccint vccint l8 vccint vccint vccint l10 vccint vccint vccint l12 vccint vccint vccint l14 vccint vccint vccint m9 vccint vccint vccint m11 vccint vccint vccint m13 vccint vccint vccint m15 vccint vccint vccint n8 vccint vccint vccint n10 vccint vccint vccint n12 vccint vccint vccint n14 vccint vccint vccint p9 vccint vccint vccint p11 vccint vccint vccint p13 vccint vccint vccint p15 vccint vccint vccint r8 vccint vccint vccint r10 vccint vccint vccint r12 vccint vccint vccint r14 vccint vccint vccint t7 vccint vccint vccint t16 vccint ta b l e 6 3 : spartan-3a dsp cs484 pinout (cont?d) bank pin name cs484 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 72 user i/os by bank table 64 and ta bl e 6 5 indicates how the user-i/o pins are distributed between the four i/o banks on the cs484 package. the awake pin is counted as a dual-purpose i/o. footprint migration differences there are no migration footprint differences between the xc3sd1800a and the xc3sd3400a in the cs484 package. ta bl e 6 4 : user i/os per bank for the xc3sd1800a in the cs484 package package edge i/o bank maximum i/os and input-only all possible i/o pins by type i/o input dual vref (1) clk to p 0 77 49 13 1 6 8 right 1 78 23 9 30 8 8 bottom 2 76 33 6 21 8 8 left 3 78 51 13 0 6 8 total 309 156 41 52 28 32 notes: 1. 19 vref are on input pins. ta bl e 6 5 : user i/os per bank for the xc3sd3400a in the cs484 package package edge i/o bank maximum i/o and input-only all possible i/o pins by type i/o input dual vref (1) clk to p 0 77 49 13 1 6 8 right 1 78 23 9 30 8 8 bottom 2 76 33 6 21 8 8 left 3 78 51 13 0 6 8 total 309 156 41 52 28 32 notes: 1. 19 vref are on input pins.
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 73 cs484 footprint left half of package (top view) 156 i/o: unrestricted, general-purpose user i/o. 41 input: unrestricted, general-purpose input pin. 51 dual: configuration pins, then possible user i/o. 28 vref: user i/o or input voltage reference for bank. 32 clk: user i/o, input, or clock buffer input. 2 config: dedicated configuration pin s. 2 suspend: dedicated suspend and dual-purpose awake power managem ent pins. 4 jtag: dedicated jtag port pins. 84 gnd: ground. 24 vcco: output voltage supply for bank. 36 vccint: internal core supply voltage (+1.2v). 24 vccaux: auxiliary supply voltage figure 15: cs484 package footprint (top view?left half) 1234567891011 a gnd prog_ b i/o l30n_0 i/o l28n_0 i/o l25n_0 i/o l25p_0 i/o l24n_0 vref_0 i/o l20p_0 gclk10 i/o l18p_0 gclk6 input i/o l15n_0 b tms vccaux i/o l30p_0 i/o l28p_0 vcco_0 i/o l24p_0 gnd i/o l20n_0 gclk11 i/o l18n_0 gclk7 vcco_0 i/o l15p_0 c i/o l02n_3 i/o l02p_3 gnd i/o l29n_0 input i/o l21p_0 i/o l26p_0 i/o l22p_0 i/o l16p_0 input input 0 vref_0 d input l04p_3 tdi input l08p_3 input l08n_3 i/o l29p_0 i/o l21n_0 i/o l26n_0 gnd i/o l22n_0 i/o l16n_0 gnd e input l04n_3 vref_3 vcco_3 i/o l09p_3 i/o l09n_3 vccaux input i/o l31p_0 vref_0 i/o l27n_0 vcco_0 input i/o l19n_0 gclk9 f i/o l06n_3 i/o l06p_3 i/o l01p_3 i/o l03p_3 i/o l03n_3 gnd i/o l31n_0 pudc_b i/o l27p_0 i/o l23n_0 i/o l19p_0 gclk8 i/o l17n_0 gclk5 g i/o l11p_3 gnd i/o l01n_3 gnd i/o l07p_3 i/o l07n_3 vccint i/o l23p_0 gnd vccaux gnd h i/o l11n_3 i/o l14p_3 i/o l05p_3 i/o l05n_3 i/o l10p_3 i/o l10n_3 gnd gnd vccint gnd vccint j i/o l14n_3 vref_3 vcco_3 input l16p_3 input l16n_3 vcco_3 input l12p_3 input l12n_3 vref_3 vccint gnd vccint gnd k i/o l19p_3 lhclk2 i/o l17p_3 i/o l17n_3 i/o l13p_3 i/o l13n_3 i/o l15p_3 vccaux gnd vccint gnd vccint l i/o l19n_3 irdy2 lhclk3 gnd i/o l20p_3 lhclk4 vccaux i/o l15n_3 i/o l18p_3 lhclk0 gnd vccint gnd vccint gnd m i/o l22p_3 vref_3 i/o l20n_3 lhclk5 input l23p_3 gnd i/o l18n_3 lhclk1 i/o l21p_3 trdy2 lhclk6 vccaux gnd vccint gnd vccint n i/o l22n_3 vcco_3 input l31p_3 input l23n_3 i/o l24n_3 i/o l24p_3 i/o l21n_3 lhclk7 vccint gnd vccint gnd p i/o l25p_3 i/o l25n_3 input l31n_3 i/o l32p_3 vref_3 vcco_3 i/o l26p_3 vccaux gnd vccint gnd vccint r i/o l28n_3 i/o l28p_3 i/o l34p_3 gnd i/o l32n_3 i/o l26n_3 gnd vccint gnd vccint gnd t i/o l30p_3 gnd input l27p_3 i/o l34n_3 i/o l29n_3 i/o l29p_3 vccint gnd vccaux gnd vccaux u i/o l30n_3 i/o l33p_3 input l27n_3 i/o l38p_3 i/o l38n_3 gnd i/o l02n_2 cso_b i/o l11n_2 i/o l10n_2 i/o l14n_2 d4 gnd v i/o l33n_3 vcco_3 i/o l36n_3 i/o l36p_3 vccaux i/o l02p_2 m2 i/o l11p_2 i/o l06n_2 vcco_2 i/o l10p_2 i/o l14p_2 d5 bank 3 bank 0 w i/o l35n_3 i/o l37n_3 i/o l37p_3 input 2 vref_2 i/o l03p_2 i/o l07n_2 vs2 gnd i/o l06p_2 input 2 vref_2 input vccaux y i/o l35p_3 input l39p_3 gnd i/o l03n_2 i/o l07p_2 rdwr_b input input i/o l13p_2 i/o l13n_2 i/o l15n_2 gclk13 i/o l15p_2 gclk12 a a input l39n_3 vref_3 vccaux i/o l01p_2 m1 i/o l04n_2 vcco_2 input gnd i/o l08n_2 vcco_2 i/o l12n_2 d6 gnd a b gnd input 2 vref_2 i/o l01n_2 m0 i/o l04p_2 i/o l05p_2 i/o l05n_2 i/o l08p_2 i/o l09p_2 vs1 i/o l09n_2 vs0 i/o l12p_2 d7 input 2 vref_2 bank 2
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 74 right half of cs484 package (top view) figure 16: cs484 package footprint (top view?right half) 12 13 14 15 16 17 18 19 20 21 22 input i/o l11p_0 i/o l10p_0 input i/o l06p_0 vref_0 i/o l06n_0 input i/o l07n_0 i/o 0 tck gnd a gnd i/o l11n_0 vcco_0 i/o l10n_0 gnd i/o l03p_0 vcco_0 i/o l02n_0 i/o l07p_0 vccaux tdo b i/o l14n_0 i/o l14p_0 input i/o l12n_0 vref_0 i/o l08n_0 i/o l03n_0 i/o l02p_0 vref_0 i/o l01n_0 gnd input l39n_1 input l39p_1 vref_1 c vccaux i/o l09n_0 i/o l12p_0 i/o l08p_0 gnd input input i/o l01p_0 i/o l36p_1 a20 i/o l37p_1 a22 i/o l37n_1 a23 d i/o l17p_0 gclk4 i/o l09p_0 vcco_0 i/o l05p_0 i/o l04p_0 input vccaux i/o l36n_1 a21 i/o l35n_1 vcco_1 i/o l33n_1 e input i/o l13n_0 i/o l13p_0 i/o l05n_0 i/o l04n_0 gnd i/o l38n_1 a25 i/o l38p_1 a24 i/o l30n_1 a19 i/o l35p_1 i/o l33p_1 f vccaux gnd vccaux gnd vccint i/o l34p_1 i/o l34n_1 i/o l30p_1 a18 input l31n_1 gnd i/o l28n_1 g gnd vccint gnd vccint gnd i/o l26p_1 a14 i/o l26n_1 a15 gnd i/o l32n_1 input l31p_1 vref_1 i/o l28p_1 h vccint gnd vccint gnd vccaux i/o l29n_1 a17 vcco_1 i/o l32p_1 i/o l25n_1 a13 input l27p_1 input l27n_1 j gnd vccint gnd vccint i/o l29p_1 a16 input l23n_1 i/o l24n_1 i/o l24p_1 i/o l25p_1 a12 vcco_1 i/o l22n_1 a11 k vccint gnd vccint gnd vccaux i/o l21n_1 rhclk7 input l23p_1 vref_1 gnd i/o l20n_1 rhclk5 i/o l20p_1 rhclk4 i/o l22p_1 a10 l gnd vccint gnd vccint gnd i/o l18n_1 rhclk1 i/o l21p_1 irdy1 rhclk6 vccaux i/o l19n_1 trdy1 rhclk3 gnd i/o l17n_1 a9 m vccint gnd vccint gnd vccaux i/o l13p_1 a2 i/o l18p_1 rhclk0 i/o l15n_1 a7 i/o l15p_1 a6 i/o l19p_1 rhclk2 i/o l17p_1 a8 n gnd vccint gnd vccint i/o l13n_1 a3 input l12n_1 vref_1 vcco_1 i/o l10p_1 input l16n_1 vcco_1 i/o l14n_1 a5 p vccint gnd vccint gnd gnd input l12p_1 i/o l10n_1 i/o l07p_1 i/o l07n_1 input l16p_1 vref_1 i/o l14p_1 a4 r gnd vccaux gnd gnd vccint i/o l05n_1 i/o l05p_1 gnd i/o l09n_1 gnd i/o l11n_1 vref_1 t i/o l17p_2 gclk0 i/o l20p_2 i/o l25p_2 i/o l25n_2 i/o l28p_2 gnd i/o l01p_1 hdc i/o l01n_1 ldc2 i/o l09p_1 input l08n_1 vref_1 i/o l11p_1 u i/o l17n_2 gclk1 i/o l20n_2 mosi csi b vcco_2 input 2 vref_2 i/o l28n_2 i/o l31n_2 cclk vccaux suspen d i/o l03n_1 a1 vcco_1 input l08p_1 v bank 0 i/o l17p_2 gclk0 i/o l20p_2 i/o l25p_2 i/o l25n_2 i/o l28p_2 gnd i/o l01p_1 hdc i/o l01n_1 ldc2 i/o l09p_1 input l08n_1 vref_1 i/o l11p_1 u i/o l17n_2 gclk1 i/o l20n_2 mosi csi b vcco_2 input 2 vref_2 i/o l28n_2 i/o l31n_2 cclk vccaux suspen d i/o l03n_1 a1 vcco_1 input l08p_1 v gnd input 2 vref_2 i/o l21n_2 i/o l24p_2 init_b gnd i/o l31p_2 d0 din/miso input 2 vref_2 i/o l03p_1 a0 input l04n_1 vref_1 input l04p_1 i/o l06p_1 w input i/o l21p_2 input 2 vref_2 i/o l24n_2 d3 i/o l29n_2 i/o l29p_2 i/o l26p_2 d2 i/o l26n_2 d1 gnd i/o l02p_1 ldc1 i/o l06n_1 y i/o l16p_2 gclk14 vcco_2 i/o l18n_2 gclk3 i/o l19p_2 gnd i/o l22p_2 awake vcco_2 i/o l27n_2 i/o l30p_2 vccaux i/o l02n_1 ldc0 a a i/o l16n_2 gclk15 i/o l18p_2 gclk2 i/o l19n_2 input i/o l22n_2 dout i/o l23p_2 i/o l23n_2 i/o l27p_2 i/o l30n_2 done gnd a b bank 2
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 75 fg676: 676-ball fine-p itch ball grid array the 676-ball fine-pitch ball grid array, fg676, supports both the xc3sd1800a and the xc3sd3400a fpgas. there are multiple pinout differences between the two devices. for a list of differences and migration advice, see the footprint migration differences section. xc3sd1800a fpga ta bl e 6 6 lists all the fg676 package pins for the xc3sd1800a fpga. they are sorted by bank number and then by pin name. pairs of pins that form a differential i/o pair appear together in the table. the table also shows the pin number for eac h pin and the pin type, as defined earlier. pinout table note: the grayed boxes denote a difference between the xc3sd1800a and the xc3sd3400a devices. ta bl e 6 6 : spartan-3a dsp fg676 pinout for xc3sd1800a fpga bank xc3sd1800a pin name fg676 ball type 0 io_l43n_0 k11 i/o 0 io_l39n_0 k12 i/o 0 io_l25p_0/gclk4 k14 gclk 0 io_l12n_0 k16 i/o 0 ip_0 j10 input 0 io_l43p_0 j11 i/o 0 io_l39p_0 j12 i/o 0 ip_0 j13 input 0 io_l25n_0/gclk5 j14 gclk 0 ip_0 j15 input 0 io_l12p_0 j16 i/o 0 ip_0/vref_0 j17 vref 0 io_l47n_0 h9 i/o 0 io_l46n_0 h10 i/o 0 io_l35n_0 h12 i/o 0 ip_0 h13 input 0 io_l16n_0 h15 i/o 0 io_l08p_0 h17 i/o 0 ip_0 h18 input 0 io_l52n_0/pudc_b g8 dual 0 io_l47p_0 g9 i/o 0 io_l46p_0 g10 i/o 0 ip_0/vref_0 g11 vref 0 io_l35p_0 g12 i/o 0 io_l27n_0/gclk9 g13 gclk 0 ip_0 g14 input 0 io_l16p_0 g15 i/o 0 io_l08n_0 g17 i/o 0 io_l02p_0/vref_0 g19 vref 0 io_l01p_0 g20 i/o 0 io_l48p_0 f7 i/o 0 io_l52p_0/vref_0 f8 vref 0 io_l31n_0 f12 i/o 0 io_l27p_0/gclk8 f13 gclk 0 io_l24n_0 f14 i/o 0 io_l20p_0 f15 i/o 0 io_l13p_0 f17 i/o 0 io_l02n_0 f19 i/o 0 io_l01n_0 f20 i/o 0 io_l48n_0 e7 i/o 0 io_l37p_0 e10 i/o 0 ip_0 e11 input 0 io_l31p_0 e12 i/o 0 io_l24p_0 e14 i/o 0 io_l20n_0/vref_0 e15 vref 0 io_l13n_0 e17 i/o 0 ip_0 e18 input 0 io_l10p_0 e21 i/o 0 io_l44n_0 d6 i/o 0 ip_0/vref_0 d7 vref 0 io_l40n_0 d8 i/o 0 io_l37n_0 d9 i/o 0 io_l34n_0 d10 i/o 0 io_l32n_0/vref_0 d11 vref 0 ip_0 d12 input 0 io_l30p_0 d13 i/o ta b l e 6 6 : spartan-3a dsp fg676 pinout for xc3sd1800a fpga (cont?d) bank xc3sd1800a pin name fg676 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 76 0 ip_0/vref_0 d14 vref 0 io_l22p_0 d16 i/o 0 io_l21p_0 d17 i/o 0 io_l17p_0 d18 i/o 0 io_l11p_0 d20 i/o 0 io_l10n_0 d21 i/o 0 io_l05p_0 d22 i/o 0 io_l06p_0 d23 i/o 0 io_l44p_0 c5 i/o 0 io_l41n_0 c6 i/o 0 io_l42n_0 c7 i/o 0 io_l40p_0 c8 i/o 0 io_l34p_0 c10 i/o 0 io_l32p_0 c11 i/o 0 io_l30n_0 c12 i/o 0 io_l28n_0/gclk11 c13 gclk 0 io_l22n_0 c15 i/o 0 io_l21n_0 c16 i/o 0 io_l19p_0 c17 i/o 0 io_l17n_0 c18 i/o 0 io_l11n_0 c20 i/o 0 io_l09p_0 c21 i/o 0 io_l05n_0 c22 i/o 0 io_l06n_0 c23 i/o 0 io_l51n_0 b3 i/o 0 io_l45n_0 b4 i/o 0 io_l41p_0 b6 i/o 0 io_l42p_0 b7 i/o 0 io_l38n_0 b8 i/o 0 io_l36n_0 b9 i/o 0 io_l33n_0 b10 i/o 0 io_l29n_0 b12 i/o 0 io_l28p_0/gclk10 b13 gclk 0 io_l26p_0/gclk6 b14 gclk 0 io_l23p_0 b15 i/o 0 io_l19n_0 b17 i/o 0 io_l18p_0 b18 i/o 0 io_l15p_0 b19 i/o 0 io_l14p_0/vref_0 b20 vref ta bl e 6 6 : spartan-3a dsp fg676 pinout for xc3sd1800a fpga (cont?d) bank xc3sd1800a pin name fg676 ball type 0 io_l09n_0 b21 i/o 0 io_l07p_0 b23 i/o 0 io_l51p_0 a3 i/o 0 io_l45p_0 a4 i/o 0 ip_0 a7 input 0 io_l38p_0 a8 i/o 0 io_l36p_0 a9 i/o 0 io_l33p_0 a10 i/o 0 io_l29p_0 a12 i/o 0 ip_0 a13 input 0 io_l26n_0/gclk7 a14 gclk 0 io_l23n_0 a15 i/o 0 ip_0 a17 input 0 io_l18n_0 a18 i/o 0 io_l15n_0 a19 i/o 0 io_l14n_0 a20 i/o 0 io_l07n_0 a22 i/o 0 ip_0 g16 input 0 ip_0 e9 input 0 ip_0 d15 input 0 ip_0 d19 input 0 ip_0 b24 input 0 ip_0 a5 input 0 ip_0 a23 input 0 ip_0 f9 input 0 ip_0 e20 input 0 ip_0 a24 input 0 ip_0 g18 input 0 ip_0 f10 input 0 ip_0 f18 input 0 ip_0 e6 input 0 ip_0 d5 input 0 ip_0 c4 input 0 vcco_0 h11 vcco 0 vcco_0 h16 vcco 0 vcco_0 e8 vcco 0 vcco_0 e13 vcco 0 vcco_0 e19 vcco 0 vcco_0 b5 vcco ta b l e 6 6 : spartan-3a dsp fg676 pinout for xc3sd1800a fpga (cont?d) bank xc3sd1800a pin name fg676 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 77 0 vcco_0 b11 vcco 0 vcco_0 b16 vcco 0 vcco_0 b22 vcco 1 io_l01p_1/hdc y20 dual 1io_l01n_1/ldc2 y21dual 1 io_l13p_1 y22 i/o 1 io_l13n_1 y23 i/o 1 io_l15p_1 y24 i/o 1 io_l15n_1 y25 i/o 1 ip_l16n_1 y26 input 1 io_l04p_1 w20 i/o 1 io_l04n_1 w21 i/o 1 io_l18p_1 w23 i/o 1 io_l08p_1 v18 i/o 1 io_l08n_1 v19 i/o 1 io_l10p_1 v21 i/o 1 io_l18n_1 v22 i/o 1 io_l21p_1 v23 i/o 1 io_l19p_1 v24 i/o 1 io_l19n_1 v25 i/o 1 ip_l20n_1/vref_1 v26 vref 1 io_l12n_1 u18 i/o 1 io_l12p_1 u19 i/o 1 io_l10n_1 u20 i/o 1 io_l14p_1 u21 i/o 1 io_l21n_1 u22 i/o 1 io_l23p_1 u23 i/o 1 io_l23n_1/vref_1 u24 vref 1 ip_l24n_1/vref_1 u26 vref 1 io_l17n_1 t17 i/o 1 io_l17p_1 t18 i/o 1 io_l14n_1 t20 i/o 1 io_l26p_1/a4 t23 dual 1 io_l26n_1/a5 t24 dual 1 io_l27n_1/a7 r17 dual 1 io_l27p_1/a6 r18 dual 1 io_l22p_1 r19 i/o 1 io_l22n_1 r20 i/o 1 io_l25p_1/a2 r21 dual ta bl e 6 6 : spartan-3a dsp fg676 pinout for xc3sd1800a fpga (cont?d) bank xc3sd1800a pin name fg676 ball type 1 io_l25n_1/a3 r22 dual 1 ip_l28p_1/vref_1 r23 vref 1 ip_l28n_1 r24 input 1 io_l29p_1/a8 r25 dual 1 io_l29n_1/a9 r26 dual 1 io_l34p_1/irdy1/rhclk6 p18 rhclk 1 io_l30n_1/rhclk1 p20 rhclk 1 io_l30p_1/rhclk0 p21 rhclk 1 io_l37p_1 p22 i/o 1 io_l33p_1/rhclk4 p23 rhclk 1 io_l31n_1/trdy1/rhclk3 p25 rhclk 1 io_l31p_1/rhclk2 p26 rhclk 1 io_l39n_1/a15 n17 dual 1 io_l39p_1/a14 n18 dual 1 io_l34n_1/rhclk7 n19 rhclk 1 io_l42p_1/a16 n20 dual 1 io_l37n_1 n21 i/o 1 ip_l36n_1 n23 input 1 io_l33n_1/rhclk5 n24 rhclk 1 ip_l32n_1 n25 input 1 ip_l32p_1 n26 input 1 io_l47n_1 m18 i/o 1 io_l47p_1 m19 i/o 1 io_l42n_1/a17 m20 dual 1 io_l45p_1 m21 i/o 1 io_l45n_1 m22 i/o 1 io_l38n_1/a13 m23 dual 1 ip_l36p_1/vref_1 m24 vref 1 io_l35n_1/a11 m25 dual 1 io_l35p_1/a10 m26 dual 1 io_l55n_1 l17 i/o 1 io_l55p_1 l18 i/o 1 io_l53p_1 l20 i/o 1 io_l50p_1 l22 i/o 1 ip_l40n_1 l23 input 1 io_l38p_1/a12 l24 dual 1 io_l57n_1 k18 i/o 1 io_l57p_1 k19 i/o 1 io_l53n_1 k20 i/o ta b l e 6 6 : spartan-3a dsp fg676 pinout for xc3sd1800a fpga (cont?d) bank xc3sd1800a pin name fg676 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 78 1 io_l50n_1 k21 i/o 1 io_l46n_1 k22 i/o 1 io_l46p_1 k23 i/o 1 ip_l40p_1 k24 input 1 io_l41p_1 k25 i/o 1 io_l41n_1 k26 i/o 1 io_l59p_1 j19 i/o 1 io_l59n_1 j20 i/o 1 io_l62p_1/a20 j21 dual 1 io_l49n_1 j22 i/o 1 io_l49p_1 j23 i/o 1 io_l43n_1/a19 j25 dual 1 io_l43p_1/a18 j26 dual 1 io_l64p_1/a24 h20 dual 1 io_l62n_1/a21 h21 dual 1 ip_l48n_1 h24 input 1 ip_l44n_1 h25 input 1 ip_l44p_1/vref_1 h26 vref 1 io_l64n_1/a25 g21 dual 1 io_l58n_1 g22 i/o 1 io_l51p_1 g23 i/o 1 io_l51n_1 g24 i/o 1 ip_l52n_1/vref_1 g25 vref 1 io_l58p_1/vref_1 f22 vref 1 io_l56n_1 f23 i/o 1 io_l54n_1 f24 i/o 1 io_l54p_1 f25 i/o 1 io_l56p_1 e24 i/o 1 io_l60p_1 e26 i/o 1 io_l61n_1 d24 i/o 1 io_l61p_1 d25 i/o 1 io_l60n_1 d26 i/o 1 io_l63n_1/a23 c25 dual 1 io_l63p_1/a22 c26 dual 1 ip_l65p_1/vref_1 b26 vref 1 io_l02p_1/ldc1 ae26 dual 1 io_l02n_1/ldc0 ad25 dual 1 io_l05p_1 ad26 i/o 1 io_l03p_1/a0 ac23 dual ta bl e 6 6 : spartan-3a dsp fg676 pinout for xc3sd1800a fpga (cont?d) bank xc3sd1800a pin name fg676 ball type 1 io_l03n_1/a1 ac24 dual 1 io_l05n_1 ac25 i/o 1 io_l06p_1 ac26 i/o 1 io_l07p_1 ab23 i/o 1 io_l07n_1/vref_1 ab24 vref 1 io_l06n_1 ab26 i/o 1 io_l09p_1 aa22 i/o 1 io_l09n_1 aa23 i/o 1 io_l11p_1 aa24 i/o 1 io_l11n_1 aa25 i/o 1 ip_l16p_1 w25 input 1 ip_l24p_1 u25 input 1 ip_l65n_1 b25 input 1 ip_l20p_1 w26 input 1 ip_l48p_1 h23 input 1 ip_l52p_1 g26 input 1 vcco_1 w22 vcco 1 vcco_1 t19 vcco 1 vcco_1 t25 vcco 1 vcco_1 n22 vcco 1 vcco_1 l19 vcco 1 vcco_1 l25 vcco 1 vcco_1 h22 vcco 1 vcco_1 e25 vcco 1 vcco_1 ab25 vcco 2 io_l02p_2/m2 y7 dual 2 io_l05n_2 y9 i/o 2 io_l12p_2 y10 i/o 2 io_l17p_2/rdwr_b y12 dual 2 io_l25n_2/gclk13 y13 gclk 2 io_l27p_2/gclk0 y14 gclk 2 io_l34n_2/d3 y15 dual 2 ip_2/vref_2 y16 vref 2 io_l43n_2 y17 i/o 2 io_l05p_2 w9 i/o 2 io_l09n_2 w10 i/o 2 io_l16n_2 w12 i/o 2 io_l20n_2 w13 i/o 2 io_l31n_2 w15 i/o ta b l e 6 6 : spartan-3a dsp fg676 pinout for xc3sd1800a fpga (cont?d) bank xc3sd1800a pin name fg676 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 79 2 io_l46p_2 w17 i/o 2 io_l09p_2 v10 i/o 2 io_l13p_2 v11 i/o 2 io_l16p_2 v12 i/o 2 io_l20p_2 v13 i/o 2 io_l31p_2 v14 i/o 2 io_l35p_2 v15 i/o 2 io_l42p_2 v16 i/o 2 io_l46n_2 v17 i/o 2 io_l13n_2 u11 i/o 2 io_l35n_2 u15 i/o 2 io_l42n_2 u16 i/o 2 io_l06n_2 af3 i/o 2 io_l07n_2 af4 i/o 2 io_l10p_2 af5 i/o 2 ip_2 af7 input 2 io_l18n_2 af8 i/o 2 io_l19n_2/vs0 af9 dual 2 io_l22n_2/d6 af10 dual 2 io_l24p_2/d5 af12 dual 2 io_l26p_2/gclk14 af13 gclk 2 io_l28p_2/gclk2 af14 gclk 2 ip_2/vref_2 af15 vref 2 ip_2/vref_2 af17 vref 2 io_l36p_2/d2 af18 dual 2 io_l37p_2 af19 i/o 2 io_l39p_2 af20 i/o 2 ip_2/vref_2 af22 vref 2 io_l48p_2 af23 i/o 2 io_l52p_2/d0/din/miso af24 dual 2 io_l51p_2 af25 i/o 2 io_l06p_2 ae3 i/o 2 io_l07p_2 ae4 i/o 2 io_l10n_2 ae6 i/o 2 io_l11n_2 ae7 i/o 2 io_l18p_2 ae8 i/o 2 io_l19p_2/vs1 ae9 dual 2 io_l22p_2/d7 ae10 dual 2 io_l24n_2/d4 ae12 dual ta bl e 6 6 : spartan-3a dsp fg676 pinout for xc3sd1800a fpga (cont?d) bank xc3sd1800a pin name fg676 ball type 2 io_l26n_2/gclk15 ae13 gclk 2 io_l28n_2/gclk3 ae14 gclk 2 io_l32n_2/dout ae15 dual 2 io_l33p_2 ae17 i/o 2 io_l36n_2/d1 ae18 dual 2 io_l37n_2 ae19 i/o 2 io_l39n_2 ae20 i/o 2 io_l44p_2 ae21 i/o 2 io_l48n_2 ae23 i/o 2 io_l52n_2/cclk ae24 dual 2 io_l51n_2 ae25 i/o 2 io_l01n_2/m0 ad4 dual 2 io_l08n_2 ad6 i/o 2 io_l11p_2 ad7 i/o 2 ip_2 ad9 input 2 ip_2 ad10 input 2 io_l23p_2 ad11 i/o 2 ip_2/vref_2 ad12 vref 2 io_l29p_2 ad14 i/o 2 io_l32p_2/awake ad15 pwrmgmt 2 ip_2 ad16 input 2 io_l33n_2 ad17 i/o 2 io_l40p_2 ad19 i/o 2 io_l41p_2 ad20 i/o 2 io_l44n_2 ad21 i/o 2 io_l45p_2 ad22 i/o 2 io_l01p_2/m1 ac4 dual 2 io_l08p_2 ac6 i/o 2 io_l14p_2 ac8 i/o 2 io_l15n_2 ac9 i/o 2 ip_2/vref_2 ac10 vref 2 io_l23n_2 ac11 i/o 2 io_l21n_2 ac12 i/o 2 ip_2 ac13 input 2 io_l29n_2 ac14 i/o 2 io_l30p_2 ac15 i/o 2 io_l38p_2 ac16 i/o 2 ip_2 ac17 input 2 io_l40n_2 ac19 i/o ta b l e 6 6 : spartan-3a dsp fg676 pinout for xc3sd1800a fpga (cont?d) bank xc3sd1800a pin name fg676 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 80 2 io_l41n_2 ac20 i/o 2 io_l45n_2 ac21 i/o 2 io_2 ac22 i/o 2 ip_2/vref_2 ab6 vref 2 io_l14n_2 ab7 i/o 2 io_l15p_2 ab9 i/o 2 io_l21p_2 ab12 i/o 2 ip_2 ab13 input 2 io_l30n_2/mosi/csi_b ab15 dual 2 io_l38n_2 ab16 i/o 2 io_l47p_2 ab18 i/o 2 io_l02n_2/cso_b aa7 dual 2 ip_2/vref_2 aa9 vref 2 io_l12n_2 aa10 i/o 2 io_l17n_2/vs2 aa12 dual 2 io_l25p_2/gclk12 aa13 gclk 2 io_l27n_2/gclk1 aa14 gclk 2 io_l34p_2/init_b aa15 dual 2 io_l43p_2 aa17 i/o 2 io_l47n_2 aa18 i/o 2 ip_2/vref_2 aa20 vref 2 ip_2 ad5 input 2 ip_2 ad23 input 2 ip_2 ac5 input 2 ip_2 ac7 input 2 ip_2 ac18 input 2 ip_2/vref_2 ab10 vref 2 ip_2 ab20 input 2 ip_2 aa19 input 2 ip_2 af2 input 2 ip_2 ab17 input 2 ip_2 y8 input 2 ip_2 y11 input 2 ip_2 y18 input 2 ip_2/vref_2 y19 vref 2 ip_2 w18 input 2 ip_2 aa8 input 2 vcco_2 w11 vcco 2 vcco_2 w16 vcco ta bl e 6 6 : spartan-3a dsp fg676 pinout for xc3sd1800a fpga (cont?d) bank xc3sd1800a pin name fg676 ball type 2 vcco_2 ae5 vcco 2 vcco_2 ae11 vcco 2 vcco_2 ae16 vcco 2 vcco_2 ae22 vcco 2 vcco_2 ab8 vcco 2 vcco_2 ab14 vcco 2 vcco_2 ab19 vcco 3 io_l53p_3 y1 i/o 3 io_l53n_3 y2 i/o 3 ip_l54p_3 y3 input 3 io_l57p_3 y5 i/o 3 io_l57n_3 y6 i/o 3 ip_l50p_3 w1 input 3 ip_l50n_3/vref_3 w2 vref 3 io_l52p_3 w3 i/o 3 io_l52n_3 w4 i/o 3 io_l63n_3 w6 i/o 3 io_l63p_3 w7 i/o 3 io_l47p_3 v1 i/o 3 io_l47n_3 v2 i/o 3 ip_l46n_3 v4 input 3 io_l49n_3 v5 i/o 3 io_l59n_3 v6 i/o 3 io_l59p_3 v7 i/o 3 io_l61n_3 v8 i/o 3 io_l44p_3 u1 i/o 3 io_l44n_3 u2 i/o 3 ip_l46p_3 u3 input 3 io_l42n_3 u4 i/o 3 io_l49p_3 u5 i/o 3 io_l51n_3 u6 i/o 3 io_l56p_3 u7 i/o 3 io_l56n_3 u8 i/o 3 io_l61p_3 u9 i/o 3 io_l38p_3 t3 i/o 3 io_l38n_3 t4 i/o 3 io_l42p_3 t5 i/o 3 io_l51p_3 t7 i/o 3 io_l48n_3 t9 i/o ta b l e 6 6 : spartan-3a dsp fg676 pinout for xc3sd1800a fpga (cont?d) bank xc3sd1800a pin name fg676 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 81 3 io_l48p_3 t10 i/o 3 io_l36p_3/vref_3 r1 vref 3 io_l36n_3 r2 i/o 3 io_l37p_3 r3 i/o 3 io_l37n_3 r4 i/o 3 io_l40p_3 r5 i/o 3 io_l40n_3 r6 i/o 3 io_l45n_3 r7 i/o 3 io_l45p_3 r8 i/o 3 io_l43n_3 r9 i/o 3 io_l43p_3/vref_3 r10 vref 3 io_l33p_3/lhclk2 p1 lhclk 3 io_l33n_3/irdy2/lhclk3 p2 lhclk 3 io_l34n_3/lhclk5 p3 lhclk 3 io_l34p_3/lhclk4 p4 lhclk 3 io_l39n_3 p6 i/o 3 io_l39p_3 p7 i/o 3 io_l41p_3 p8 i/o 3 io_l41n_3 p9 i/o 3 io_l35n_3/lhclk7 p10 lhclk 3 io_l31p_3 n1 i/o 3 io_l31n_3 n2 i/o 3 io_l30n_3 n4 i/o 3 io_l30p_3 n5 i/o 3 io_l32p_3/lhclk0 n6 lhclk 3 io_l32n_3/lhclk1 n7 lhclk 3 io_l35p_3/trdy2/lhclk6 n9 lhclk 3 io_l29n_3/vref_3 m1 vref 3 io_l29p_3 m2 i/o 3 io_l27n_3 m3 i/o 3 io_l27p_3 m4 i/o 3 io_l28p_3 m5 i/o 3 io_l28n_3 m6 i/o 3 io_l26n_3 m7 i/o 3 io_l26p_3 m8 i/o 3 io_l21n_3 m9 i/o 3 io_l21p_3 m10 i/o 3 io_l25n_3 l3 i/o 3 io_l25p_3 l4 i/o ta bl e 6 6 : spartan-3a dsp fg676 pinout for xc3sd1800a fpga (cont?d) bank xc3sd1800a pin name fg676 ball type 3 io_l18n_3 l7 i/o 3 io_l15n_3 l9 i/o 3 io_l15p_3 l10 i/o 3 ip_l24n_3 k1 input 3 io_l23n_3 k2 i/o 3 io_l23p_3 k3 i/o 3 io_l22n_3 k4 i/o 3 io_l22p_3 k5 i/o 3 io_l18p_3 k6 i/o 3 io_l13p_3 k7 i/o 3 io_l05n_3 k8 i/o 3 io_l05p_3 k9 i/o 3 ip_l24p_3 j1 input 3 ip_l20n_3/vref_3 j2 vref 3 ip_l20p_3 j3 input 3 io_l19n_3 j4 i/o 3 io_l19p_3 j5 i/o 3 io_l13n_3 j6 i/o 3 io_l10p_3 j7 i/o 3 io_l01p_3 j8 i/o 3 io_l01n_3 j9 i/o 3 io_l17n_3 h1 i/o 3 io_l17p_3 h2 i/o 3 ip_l12n_3/vref_3 h4 vref 3 io_l10n_3 h6 i/o 3 io_l03n_3 h7 i/o 3 ip_l16n_3 g1 input 3 io_l14p_3 g3 i/o 3 io_l09n_3 g4 i/o 3 io_l03p_3 g6 i/o 3 io_l11n_3 f2 i/o 3 io_l14n_3 f3 i/o 3 io_l07n_3 f4 i/o 3 io_l09p_3 f5 i/o 3 io_l11p_3 e1 i/o 3 io_l07p_3 e3 i/o 3 io_l06n_3 e4 i/o 3 io_l06p_3 d3 i/o 3 ip_l04n_3/vref_3 c1 vref ta b l e 6 6 : spartan-3a dsp fg676 pinout for xc3sd1800a fpga (cont?d) bank xc3sd1800a pin name fg676 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 82 3 ip_l04p_3 c2 input 3 io_l02n_3 b1 i/o 3 io_l02p_3 b2 i/o 3 ip_l66p_3 ae1 input 3 ip_l66n_3/vref_3 ae2 vref 3 io_l65p_3 ad1 i/o 3 io_l65n_3 ad2 i/o 3 io_l60n_3 ac1 i/o 3 io_l64p_3 ac2 i/o 3 io_l64n_3 ac3 i/o 3 io_l60p_3 ab1 i/o 3 io_l55p_3 aa2 i/o 3 io_l55n_3 aa3 i/o 3 ip_l58n_3/vref_3 aa5 vref 3 ip_l16p_3 g2 input 3 ip_l12p_3 g5 input 3 ip_l08p_3 d2 input 3 ip_l62p_3 ab3 input 3 ip_l58p_3 aa4 input 3 ip_l08n_3 d1 input 3 ip_l62n_3 ab4 input 3 ip_l54n_3 y4 input 3 vcco_3 w5 vcco 3 vcco_3 t2 vcco 3 vcco_3 t8 vcco 3 vcco_3 p5 vcco 3 vcco_3 l2 vcco 3 vcco_3 l8 vcco 3 vcco_3 h5 vcco 3 vcco_3 e2 vcco 3 vcco_3 ab2 vcco gnd gnd w8 gnd gnd gnd w14 gnd gnd gnd w19 gnd gnd gnd w24 gnd gnd gnd v3 gnd gnd gnd u10 gnd gnd gnd u13 gnd gnd gnd u17 gnd ta bl e 6 6 : spartan-3a dsp fg676 pinout for xc3sd1800a fpga (cont?d) bank xc3sd1800a pin name fg676 ball type gnd gnd t1 gnd gnd gnd t6 gnd gnd gnd t12 gnd gnd gnd t14 gnd gnd gnd t16 gnd gnd gnd t21 gnd gnd gnd t26 gnd gnd gnd r11 gnd gnd gnd r13 gnd gnd gnd r15 gnd gnd gnd p12 gnd gnd gnd p16 gnd gnd gnd p19 gnd gnd gnd p24 gnd gnd gnd n3 gnd gnd gnd n8 gnd gnd gnd n11 gnd gnd gnd n15 gnd gnd gnd m12 gnd gnd gnd m14 gnd gnd gnd m16 gnd gnd gnd l1 gnd gnd gnd l6 gnd gnd gnd l11 gnd gnd gnd l13 gnd gnd gnd l15 gnd gnd gnd l21 gnd gnd gnd l26 gnd gnd gnd k10 gnd gnd gnd k17 gnd gnd gnd j24 gnd gnd gnd h3 gnd gnd gnd h8 gnd gnd gnd h14 gnd gnd gnd h19 gnd gnd gnd f1 gnd gnd gnd f6 gnd gnd gnd f11 gnd gnd gnd f16 gnd ta b l e 6 6 : spartan-3a dsp fg676 pinout for xc3sd1800a fpga (cont?d) bank xc3sd1800a pin name fg676 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 83 gnd gnd f21 gnd gnd gnd f26 gnd gnd gnd c3 gnd gnd gnd c9 gnd gnd gnd c14 gnd gnd gnd c19 gnd gnd gnd c24 gnd gnd gnd af1 gnd gnd gnd af6 gnd gnd gnd af11 gnd gnd gnd af16 gnd gnd gnd af21 gnd gnd gnd af26 gnd gnd gnd ad3 gnd gnd gnd ad8 gnd gnd gnd ad13 gnd gnd gnd ad18 gnd gnd gnd ad24 gnd gnd gnd aa1 gnd gnd gnd aa6 gnd gnd gnd aa11 gnd gnd gnd aa16 gnd gnd gnd aa21 gnd gnd gnd aa26 gnd gnd gnd a1 gnd gnd gnd a6 gnd gnd gnd a11 gnd gnd gnd a16 gnd gnd gnd a21 gnd gnd gnd a26 gnd vccaux suspend v20 pwrmgmt vccaux done ab21 config vccaux prog_b a2 config vccaux tdi g7 jtag vccaux tdo e23 jtag vccaux tms d4 jtag vccaux tck a25 jtag vccaux vccaux v9 vccaux vccaux vccaux u14 vccaux ta bl e 6 6 : spartan-3a dsp fg676 pinout for xc3sd1800a fpga (cont?d) bank xc3sd1800a pin name fg676 ball type vccaux vccaux t22 vccaux vccaux vccaux p17 vccaux vccaux vccaux n10 vccaux vccaux vccaux l5 vccaux vccaux vccaux k13 vccaux vccaux vccaux j18 vccaux vccaux vccaux e5 vccaux vccaux vccaux e16 vccaux vccaux vccaux e22 vccaux vccaux vccaux ab5 vccaux vccaux vccaux ab11 vccaux vccaux vccaux ab22 vccaux vccint vccint u12 vccint vccint vccint t11 vccint vccint vccint t13 vccint vccint vccint t15 vccint vccint vccint r12 vccint vccint vccint r14 vccint vccint vccint r16 vccint vccint vccint p11 vccint vccint vccint p13 vccint vccint vccint p14 vccint vccint vccint p15 vccint vccint vccint n12 vccint vccint vccint n13 vccint vccint vccint n14 vccint vccint vccint n16 vccint vccint vccint m11 vccint vccint vccint m13 vccint vccint vccint m15 vccint vccint vccint m17 vccint vccint vccint l12 vccint vccint vccint l14 vccint vccint vccint l16 vccint vccint vccint k15 vccint ta b l e 6 6 : spartan-3a dsp fg676 pinout for xc3sd1800a fpga (cont?d) bank xc3sd1800a pin name fg676 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 84 user i/os by bank table 67 indicates how the available user-i/o pins are distributed between the four i/o banks on the fg676 package. the awake pin is counted as a dual-purpose i/o. ta bl e 6 7 : user i/os per bank for the xc3sd1800a in the fg676 package package edge i/o bank maximum i/os and input-only all possible i/o pins by type i/o input dual vref (1) clk to p 0 128 82 28 1 9 8 right 1 130 67 15 30 10 8 bottom 2 129 68 21 21 11 8 left 3 132 97 18 0 9 8 total 519 314 82 52 39 32 notes: 1. 28 vref are on input pins.
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 85 fg676 footprint ? xc3sd1800a fpga left half of package (top view) 314 i/o: unrestricted, general-purpose user i/o. 82 input: unrestricted, general-purpose input pin. 51 dual: configuration pins, then possible user i/o. 39 vref: user i/o or input voltage reference for bank. 32 clk: user i/o, input, or clock buffer input. 2 config: dedicated configuration pins . 4 jtag: dedicated jtag port pins. 2 suspend: dedicated suspend and dual-purpose awake power management pins 77 gnd: ground 36 vcco: output voltage supply for bank. 23 vccint: internal core supply voltage (+1.2v). 14 vccaux: auxiliary supply voltage. note: the boxes with triangles inside indicate pin differences from the xc3sd3400a device. please see the footprint migration differences section for more information. figure 16: fg676 package footprint for xc3sd1800a fpga (top view?left half) 12345678910111213 a gnd prog_ b i/o l51p_0 i/o l45p_0 input ? gnd input ? i/o l38p_0 i/o l36p_0 i/o l33p_0 gnd i/o l29p_0 input b i/o l02n_3 i/o l02p_3 i/o l51n_0 i/o l45n_0 vcco_0 i/o l41p_0 i/o l42p_0 i/o l38n_0 i/o l36n_0 i/o l33n_0 vcco_0 i/o l29n_0 i/o l28p_0 gclk10 c input l04n_3 vref_3 ? input l04p_3 ? gnd input ? i/o l44p_0 i/o l41n_0 i/o l42n_0 i/o l40p_0 gnd i/o l34p_0 i/o l32p_0 i/o l30n_0 i/o l28n_0 gclk11 d input l08n_3 ? input l08p_3 ? i/o l06p_3 tms input ? l44n_0 input vref_0 i/o l40n_0 i/o l37n_0 i/o l34n_0 i/o l32n_0 vref_0 input i/o l30p_0 e i/o l11p_3 vcco_3 i/o l07p_3 i/o l06n_3 vccaux input ? l48n_0 vcco_0 input ? l37p_0 input i/o l31p_0 vcco_0 f gnd i/o l11n_3 i/o l14n_3 i/o l07n_3 i/o l09p_3 gnd i/o l48p_0 i/o l52p_0 vref_0 input ? ? gnd i/o l31n_0 i/o l27p_0 gclk8 g input l16n_3 ? input l16p_3 ? i/o l14p_3 i/o l09n_3 input l12p_3 ? i/o l03p_3 tdi i/o l52n_0 pudc_b i/o l47p_0 i/o l46p_0 input vref_0 i/o l35p_0 i/o l27n_0 gclk9 h i/o l17n_3 i/o l17p_3 gnd input l12n_3 vref_3 ? i/o l10n_3 i/o l03n_3 gnd i/o l47n_0 i/o l46n_0 vcco_0 i/o l35n_0 input j input l24p_3 input l20n_3 vref_3 input l20p_3 i/o l19n_3 i/o l19p_3 i/o l13n_3 i/o l10p_3 i/o l01p_3 i/o l01n_3 input i/o l43p_0 i/o l39p_0 input k input l24n_3 i/o l23n_3 i/o l23p_3 i/o l22n_3 i/o l22p_3 i/o l18p_3 i/o l13p_3 i/o l05n_3 i/o l05p_3 gnd i/o l43n_0 i/o l39n_0 vccaux l gnd vcco_3 i/o l25n_3 i/o l25p_3 vccaux gnd i/o l18n_3 vcco_3 i/o l15n_3 i/o l15p_3 gnd vccint gnd m i/o l29n_3 vref_3 i/o l29p_3 i/o l27n_3 i/o l27p_3 i/o l28p_3 i/o l28n_3 i/o l26n_3 i/o l26p_3 i/o l21n_3 i/o l21p_3 vccint gnd vccint n i/o l31p_3 i/o l31n_3 gnd i/o l30n_3 i/o l30p_3 i/o l32p_3 lhclk0 i/o l32n_3 lhclk1 gnd i/o l35p_3 trdy2 lhclk6 vccaux gnd vccint vccint p i/o l33p_3 lhclk2 i/o l33n_3 irdy2 lhclk3 i/o l34n_3 lhclk5 i/o l34p_3 lhclk4 vcco_3 i/o l39n_3 i/o l39p_3 i/o l41p_3 i/o l41n_3 i/o l35n_3 lhclk7 vccint gnd vccint r i/o l36p_3 vref_3 i/o l36n_3 i/o l37p_3 i/o l37n_3 i/o l40p_3 i/o l40n_3 i/o l45n_3 i/o l45p_3 i/o l43n_3 i/o l43p_3 vref_3 gnd vccint gnd t gnd vcco_3 i/o l38p_3 i/o l38n_3 i/o l42p_3 gnd i/o l51p_3 vcco_3 i/o l48n_3 i/o l48p_3 vccint gnd vccint u i/o l44p_3 i/o l44n_3 input l46p_3 i/o l42n_3 i/o l49p_3 i/o l51n_3 i/o l56p_3 i/o l56n_3 i/o l61p_3 gnd i/o l13n_2 vccint gnd bank 0 bank 3 v i/o l47p_3 i/o l47n_3 gnd input l46n_3 i/o l49n_3 i/o l59n_3 i/o l59p_3 i/o l61n_3 vccaux i/o l09p_2 i/o l13p_2 i/o l16p_2 i/o l20p_2 w input l50p_3 input l50n_3 vref_3 i/o l52p_3 i/o l52n_3 vcco_3 i/o l63n_3 i/o l63p_3 gnd i/o l05p_2 i/o l09n_2 vcco_2 i/o l16n_2 i/o l20n_2 y i/o l53p_3 i/o l53n_3 input l54p_3 ? input l54n_3 ? i/o l57p_3 i/o l57n_3 i/o l02p_2 m2 input ? l05n_2 i/o l12p_2 input ? l17p_2 rdwr_b i/o l25n_2 gclk13 a a gnd i/o l55p_3 i/o l55n_3 input l58p_3 ? input l58n_3 vref_3 ? gnd i/o l02n_2 cso_b input ? vref_2 i/o l12n_2 gnd i/o l17n_2 vs2 i/o l25p_2 gclk12 a b i/o l60p_3 vcco_3 input l62p_3 ? input l62n_3 ? vccaux input vref_2 i/o l14n_2 vcco_2 i/o l15p_2 input vref_2 ? vccaux i/o l21p_2 input a c i/o l60n_3 i/o l64p_3 i/o l64n_3 i/o l01p_2 m1 input ? l08p_2 input ? l14p_2 i/o l15n_2 input vref_2 i/o l23n_2 i/o l21n_2 input a d i/o l65p_3 i/o l65n_3 gnd i/o l01n_2 m0 input ? l08n_2 i/o l11p_2 gnd input input i/o l23p_2 input vref_2 gnd a e input l66p_3 input l66n_3 vref_3 i/o l06p_2 i/o l07p_2 vcco_2 i/o l10n_2 i/o l11n_2 i/o l18p_2 i/o l19p_2 vs1 i/o l22p_2 d7 vcco_2 i/o l24n_2 d4 i/o l26n_2 gclk15 a f gnd input ? l06n_2 i/o l07n_2 i/o l10p_2 gnd input ? l18n_2 i/o l19n_2 vs0 i/o l22n_2 d6 gnd i/o l24p_2 d5 i/o l26p_2 gclk14 bank 2
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 86 right half of fg676 package (top view) figure 17: fg676 package footprint for xc 3sd1800a fpga (top view?right half) 14 15 16 17 18 19 20 21 22 23 24 25 26 i/o l26n_0 gclk7 i/o l23n_0 gnd input i/o l18n_0 i/o l15n_0 i/o l14n_0 gnd i/o l07n_0 input ? ? tck gnd a i/o l26p_0 gclk6 i/o l23p_0 vcco_0 i/o l19n_0 i/o l18p_0 i/o l15p_0 i/o l14p_0 vref_0 i/o l09n_0 vcco_0 i/o l07p_0 input ? l65n_1 ? input l65p_1 vref_1 ? b gnd i/o l22n_0 i/o l21n_0 i/o l19p_0 i/o l17n_0 gnd i/o l11n_0 i/o l09p_0 i/o l05n_0 i/o l06n_0 gnd i/o l63n_1 a23 i/o l63p_1 a22 c input vref_0 input ? l22p_0 i/o l21p_0 i/o l17p_0 input ? l11p_0 i/o l10n_0 i/o l05p_0 i/o l06p_0 i/o l61n_1 i/o l61p_1 i/o l60n_1 d i/o l24p_0 i/o l20n_0 vref_0 vccaux i/o l13n_0 input vcco_0 input ? l10p_0 vccaux tdo i/o l56p_1 vcco_1 i/o l60p_1 e i/o l24n_0 i/o l20p_0 gnd i/o l13p_0 input ? l02n_0 i/o l01n_0 gnd i/o l58p_1 vref_1 i/o l56n_1 i/o l54n_1 i/o l54p_1 gnd f input i/o l16p_0 input ? l08n_0 input ? l02p_0 vref_0 i/o l01p_0 i/o l64n_1 a25 i/o l58n_1 i/o l51p_1 i/o l51n_1 input l52n_1 vref_1 ? input l52p_1 ? g gnd i/o l16n_0 vcco_0 i/o l08p_0 input gnd i/o l64p_1 a24 i/o l62n_1 a21 vcco_1 input l48p_1 ? input l48n_1 ? input l44n_1 ? input l44p_1 vref_1 ? h i/o l25n_0 gclk5 input i/o l12p_0 input vref_0 vccaux i/o l59p_1 i/o l59n_1 i/o l62p_1 a20 i/o l49n_1 i/o l49p_1 gnd i/o l43n_1 a19 i/o l43p_1 a18 j i/o l25p_0 gclk4 vccint i/o l12n_0 gnd i/o l57n_1 i/o l57p_1 i/o l53n_1 i/o l50n_1 i/o l46n_1 i/o l46p_1 input l40p_1 i/o l41p_1 i/o l41n_1 k vccint gnd vccint i/o l55n_1 i/o l55p_1 vcco_1 i/o l53p_1 gnd i/o l50p_1 input l40n_1 i/o l38p_1 a12 vcco_1 gnd l gnd vccint gnd vccint i/o l47n_1 i/o l47p_1 i/o l42n_1 a17 i/o l45p_1 i/o l45n_1 i/o l38n_1 a13 input l36p_1 vref_1 i/o l35n_1 a11 i/o l35p_1 a10 m vccint gnd vccint i/o l39n_1 a15 i/o l39p_1 a14 i/o l34n_1 rhclk7 i/o l42p_1 a16 i/o l37n_1 vcco_1 input l36n_1 i/o l33n_1 rhclk5 input l32n_1 input l32p_1 n vccint vccint gnd vccaux i/o l34p_1 irdy1 rhclk6 gnd i/o l30n_1 rhclk1 i/o l30p_1 rhclk0 i/o l37p_1 i/o l33p_1 rhclk4 gnd i/o l31n_1 trdy1 rhclk3 i/o l31p_1 rhclk2 p vccint gnd vccint i/o l27n_1 a7 i/o l27p_1 a6 i/o l22p_1 i/o l22n_1 i/o l25p_1 a2 i/o l25n_1 a3 input l28p_1 vref_1 input l28n_1 i/o l29p_1 a8 i/o l29n_1 a9 r gnd vccint gnd i/o l17n_1 i/o l17p_1 vcco_1 i/o l14n_1 gnd vccaux i/o l26p_1 a4 i/o l26n_1 a5 vcco_1 gnd t vccaux i/o l35n_2 i/o l42n_2 gnd i/o l12n_1 i/o l12p_1 i/o l10n_1 i/o l14p_1 i/o l21n_1 i/o l23p_1 i/o l23n_1 vref_1 input l24p_1 ? input l24n_1 vref_1 ? u bank 0 bank 1 i/o l31p_2 i/o l35p_2 i/o l42p_2 i/o l46n_2 i/o l08p_1 i/o l08n_1 suspend i/o l10p_1 i/o l18n_1 i/o l21p_1 i/o l19p_1 i/o l19n_1 input l20n_1 vref_1 ? v gnd i/o l31n_2 vcco_2 i/o l46p_2 input ? gnd i/o l04p_1 i/o l04n_1 vcco_1 i/o l18p_1 gnd input l16p_1 ? input l20p_1 ? w i/o l27p_2 gclk0 i/o l34n_2 d3 input vref_2 i/o l43n_2 input ? vref_2 ? i/o l01p_1 hdc i/o l01n_1 ldc2 i/o l13p_1 i/o l13n_1 i/o l15p_1 i/o l15n_1 input l16n_1 ? y i/o l27n_2 gclk1 i/o l34p_2 init_b gnd i/o l43p_2 i/o l47n_2 input ? vref_2 gnd i/o l09p_1 i/o l09n_1 i/o l11p_1 i/o l11n_1 gnd a a vcco_2 i/o l30n_2 mosi csi _ b i/o l38n_2 input ? l47p_2 vcco_2 input ? done vccaux i/o l07p_1 i/o l07n_1 vref_1 vcco_1 i/o l06n_1 a b i/o l29n_2 i/o l30p_2 i/o l38p_2 input input ? l40n_2 i/o l41n_2 i/o l45n_2 i/o 2 i/o l03p_1 a0 i/o l03n_1 a1 i/o l05n_1 i/o l06p_1 a c i/o l29p_2 i/o l32p_2 awake input i/o l33n_2 gnd i/o l40p_2 i/o l41p_2 i/o l44n_2 i/o l45p_2 input ? gnd i/o l02n_1 ldc0 i/o l05p_1 a d i/o l28n_2 gclk3 i/o l32n_2 dout vcco_2 i/o l33p_2 i/o l36n_2 d1 i/o l37n_2 i/o l39n_2 i/o l44p_2 vcco_2 i/o l48n_2 i/o l52n_2 cclk i/o l51n_2 i/o l02p_1 ldc1 a e i/o l28p_2 gclk2 input vref_2 gnd input vref_2 i/o l36p_2 d2 i/o l37p_2 i/o l39p_2 gnd input vref_2 i/o l48p_2 i/o l52p_2 d0 din/miso i/o l51p_2 gnd a f bank 2
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 87 xc3sd3400a fpga ta bl e 6 8 lists all the fg676 package pins for the xc3sd3400a fpga. they are sorted by bank number and then by pin name. pairs of pins that form a differential i/o pair appear together in the table. ta b l e 6 8 also shows the pin number for each pin and the pin type, as defined earlier. an electronic version of this package pinout table and fo otprint diagram is available for do wnload from the xilinx website at: www.xilinx.com/support/documentat ion/data_sheets/s3a_pin.zip . pinout table note: the grayed boxes denote a difference between the xc3sd1800a and the xc3sd3400a devices. ta bl e 6 8 : spartan-3a dsp fg676 pinout for xc3sd3400a fpga bank xc3sd3400a pin name fg676 ball type 0 io_l43n_0 k11 i/o 0 io_l39n_0 k12 i/o 0 io_l25p_0/gclk4 k14 gclk 0 io_l12n_0 k16 i/o 0 ip_0 j10 input 0 io_l43p_0 j11 i/o 0 io_l39p_0 j12 i/o 0 ip_0 j13 input 0 io_l25n_0/gclk5 j14 gclk 0 ip_0 j15 input 0 io_l12p_0 j16 i/o 0 ip_0/vref_0 j17 vref 0 io_l47n_0 h9 i/o 0 io_l46n_0 h10 i/o 0 io_l35n_0 h12 i/o 0 ip_0 h13 input 0 io_l16n_0 h15 i/o 0 io_l08p_0 h17 i/o 0 ip_0 h18 input 0 io_l52n_0/pudc_b g8 dual 0 io_l47p_0 g9 i/o 0 io_l46p_0 g10 i/o 0 ip_0/vref_0 g11 vref 0 io_l35p_0 g12 i/o 0 io_l27n_0/gclk9 g13 gclk 0 ip_0 g14 input 0 io_l16p_0 g15 i/o 0 io_l08n_0 g17 i/o 0 io_l02p_0/vref_0 g19 vref 0 io_l01p_0 g20 i/o 0 io_l48p_0 f7 i/o 0 io_l52p_0/vref_0 f8 vref 0 io_l31n_0 f12 i/o 0 io_l27p_0/gclk8 f13 gclk 0 io_l24n_0 f14 i/o 0 io_l20p_0 f15 i/o 0 io_l13p_0 f17 i/o 0 io_l02n_0 f19 i/o 0 io_l01n_0 f20 i/o 0 io_l48n_0 e7 i/o 0 io_l37p_0 e10 i/o 0 ip_0 e11 input 0 io_l31p_0 e12 i/o 0 io_l24p_0 e14 i/o 0 io_l20n_0/vref_0 e15 vref 0 io_l13n_0 e17 i/o 0 ip_0 e18 input 0 io_l10p_0 e21 i/o 0 io_l44n_0 d6 i/o 0 ip_0/vref_0 d7 vref 0 io_l40n_0 d8 i/o 0 io_l37n_0 d9 i/o 0 io_l34n_0 d10 i/o 0 io_l32n_0/vref_0 d11 vref 0 ip_0 d12 input 0 io_l30p_0 d13 i/o 0 ip_0/vref_0 d14 vref 0 io_l22p_0 d16 i/o 0 io_l21p_0 d17 i/o 0 io_l17p_0 d18 i/o 0 io_l11p_0 d20 i/o ta b l e 6 8 : spartan-3a dsp fg676 pinout for xc3sd3400a fpga (cont?d) bank xc3sd3400a pin name fg676 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 88 0 io_l10n_0 d21 i/o 0 io_l05p_0 d22 i/o 0 io_l06p_0 d23 i/o 0 io_l44p_0 c5 i/o 0 io_l41n_0 c6 i/o 0 io_l42n_0 c7 i/o 0 io_l40p_0 c8 i/o 0 io_l34p_0 c10 i/o 0 io_l32p_0 c11 i/o 0 io_l30n_0 c12 i/o 0 io_l28n_0/gclk11 c13 gclk 0 io_l22n_0 c15 i/o 0 io_l21n_0 c16 i/o 0 io_l19p_0 c17 i/o 0 io_l17n_0 c18 i/o 0 io_l11n_0 c20 i/o 0 io_l09p_0 c21 i/o 0 io_l05n_0 c22 i/o 0 io_l06n_0 c23 i/o 0 io_l51n_0 b3 i/o 0 io_l45n_0 b4 i/o 0 io_l41p_0 b6 i/o 0 io_l42p_0 b7 i/o 0 io_l38n_0 b8 i/o 0 io_l36n_0 b9 i/o 0 io_l33n_0 b10 i/o 0 io_l29n_0 b12 i/o 0 io_l28p_0/gclk10 b13 gclk 0 io_l26p_0/gclk6 b14 gclk 0 io_l23p_0 b15 i/o 0 io_l19n_0 b17 i/o 0 io_l18p_0 b18 i/o 0 io_l15p_0 b19 i/o 0 io_l14p_0/vref_0 b20 vref 0 io_l09n_0 b21 i/o 0 io_l07p_0 b23 i/o 0 io_l51p_0 a3 i/o 0 io_l45p_0 a4 i/o 0 io_l38p_0 a8 i/o ta bl e 6 8 : spartan-3a dsp fg676 pinout for xc3sd3400a fpga (cont?d) bank xc3sd3400a pin name fg676 ball type 0 io_l36p_0 a9 i/o 0 io_l33p_0 a10 i/o 0 io_l29p_0 a12 i/o 0 ip_0 a13 input 0 io_l26n_0/gclk7 a14 gclk 0 io_l23n_0 a15 i/o 0 ip_0 a17 input 0 io_l18n_0 a18 i/o 0 io_l15n_0 a19 i/o 0 io_l14n_0 a20 i/o 0 io_l07n_0 a22 i/o 0 vcco_0 h11 vcco 0 vcco_0 h16 vcco 0 vcco_0 e8 vcco 0 vcco_0 e13 vcco 0 vcco_0 e19 vcco 0 vcco_0 b5 vcco 0 vcco_0 b11 vcco 0 vcco_0 b16 vcco 0 vcco_0 b22 vcco 0 vcco_0 a7 vcco 1 io_l01p_1/hdc y20 dual 1 io_l01n_1/ldc2 y21 dual 1 io_l13p_1 y22 i/o 1 io_l13n_1 y23 i/o 1 io_l15p_1 y24 i/o 1 io_l15n_1 y25 i/o 1 ip_1 y26 input 1 io_l04p_1 w20 i/o 1 io_l04n_1 w21 i/o 1 io_l18p_1 w23 i/o 1 io_l08p_1 v18 i/o 1 io_l08n_1 v19 i/o 1 io_l10p_1 v21 i/o 1 io_l18n_1 v22 i/o 1 io_l21p_1 v23 i/o 1 io_l19p_1 v24 i/o 1 io_l19n_1 v25 i/o 1 ip_1/vref_1 v26 vref ta b l e 6 8 : spartan-3a dsp fg676 pinout for xc3sd3400a fpga (cont?d) bank xc3sd3400a pin name fg676 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 89 1 io_l12n_1 u18 i/o 1 io_l12p_1 u19 i/o 1 io_l10n_1 u20 i/o 1 io_l14p_1 u21 i/o 1 io_l21n_1 u22 i/o 1 io_l23p_1 u23 i/o 1 io_l23n_1/vref_1 u24 vref 1 ip_1/vref_1 u26 vref 1 io_l17n_1 t17 i/o 1 io_l17p_1 t18 i/o 1 io_l14n_1 t20 i/o 1 io_l26p_1/a4 t23 dual 1 io_l26n_1/a5 t24 dual 1 io_l27n_1/a7 r17 dual 1 io_l27p_1/a6 r18 dual 1 io_l22p_1 r19 i/o 1 io_l22n_1 r20 i/o 1 io_l25p_1/a2 r21 dual 1 io_l25n_1/a3 r22 dual 1 ip_l28p_1/vref_1 r23 vref 1 ip_l28n_1 r24 input 1 io_l29p_1/a8 r25 dual 1 io_l29n_1/a9 r26 dual 1 io_l34p_1/irdy1/rhclk6 p18 rhclk 1 io_l30n_1/rhclk1 p20 rhclk 1 io_l30p_1/rhclk0 p21 rhclk 1 io_l37p_1 p22 i/o 1 io_l33p_1/rhclk4 p23 rhclk 1 io_l31n_1/trdy1/rhclk3 p25 rhclk 1 io_l31p_1/rhclk2 p26 rhclk 1 io_l39n_1/a15 n17 dual 1 io_l39p_1/a14 n18 dual 1 io_l34n_1/rhclk7 n19 rhclk 1 io_l42p_1/a16 n20 dual 1 io_l37n_1 n21 i/o 1 ip_l36n_1 n23 input 1 io_l33n_1/rhclk5 n24 rhclk 1 ip_l32n_1 n25 input 1 ip_l32p_1 n26 input ta bl e 6 8 : spartan-3a dsp fg676 pinout for xc3sd3400a fpga (cont?d) bank xc3sd3400a pin name fg676 ball type 1 io_l47n_1 m18 i/o 1 io_l47p_1 m19 i/o 1 io_l42n_1/a17 m20 dual 1 io_l45p_1 m21 i/o 1 io_l45n_1 m22 i/o 1 io_l38n_1/a13 m23 dual 1 ip_l36p_1/vref_1 m24 vref 1 io_l35n_1/a11 m25 dual 1 io_l35p_1/a10 m26 dual 1 io_l55n_1 l17 i/o 1 io_l55p_1 l18 i/o 1 io_l53p_1 l20 i/o 1 io_l50p_1 l22 i/o 1 ip_l40n_1 l23 input 1 io_l38p_1/a12 l24 dual 1 io_l57n_1 k18 i/o 1 io_l57p_1 k19 i/o 1 io_l53n_1 k20 i/o 1 io_l50n_1 k21 i/o 1 io_l46n_1 k22 i/o 1 io_l46p_1 k23 i/o 1 ip_l40p_1 k24 input 1 io_l41p_1 k25 i/o 1 io_l41n_1 k26 i/o 1 io_l59p_1 j19 i/o 1 io_l59n_1 j20 i/o 1 io_l62p_1/a20 j21 dual 1 io_l49n_1 j22 i/o 1 io_l49p_1 j23 i/o 1 io_l43n_1/a19 j25 dual 1 io_l43p_1/a18 j26 dual 1 io_l64p_1/a24 h20 dual 1 io_l62n_1/a21 h21 dual 1 ip_1 h24 input 1 ip_1/vref_1 h26 vref 1 io_l64n_1/a25 g21 dual 1 io_l58n_1 g22 i/o 1 io_l51p_1 g23 i/o 1 io_l51n_1 g24 i/o ta b l e 6 8 : spartan-3a dsp fg676 pinout for xc3sd3400a fpga (cont?d) bank xc3sd3400a pin name fg676 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 90 1 ip_1/vref_1 g25 vref 1 io_l58p_1/vref_1 f22 vref 1 io_l56n_1 f23 i/o 1 io_l54n_1 f24 i/o 1 io_l54p_1 f25 i/o 1 io_l56p_1 e24 i/o 1 io_l60p_1 e26 i/o 1 io_l61n_1 d24 i/o 1 io_l61p_1 d25 i/o 1 io_l60n_1 d26 i/o 1 io_l63n_1/a23 c25 dual 1 io_l63p_1/a22 c26 dual 1 ip_1/vref_1 b26 vref 1 io_l02p_1/ldc1 ae26 dual 1 io_l02n_1/ldc0 ad25 dual 1 io_l05p_1 ad26 i/o 1 io_l03p_1/a0 ac23 dual 1 io_l03n_1/a1 ac24 dual 1 io_l05n_1 ac25 i/o 1 io_l06p_1 ac26 i/o 1 io_l07p_1 ab23 i/o 1 io_l07n_1/vref_1 ab24 vref 1 io_l06n_1 ab26 i/o 1 io_l09p_1 aa22 i/o 1 io_l09n_1 aa23 i/o 1 io_l11p_1 aa24 i/o 1 io_l11n_1 aa25 i/o 1 vcco_1 w22 vcco 1 vcco_1 t19 vcco 1 vcco_1 t25 vcco 1 vcco_1 n22 vcco 1 vcco_1 l19 vcco 1 vcco_1 l25 vcco 1 vcco_1 h22 vcco 1 vcco_1 h25 vcco 1 vcco_1 e25 vcco 1 vcco_1 ab25 vcco 2 io_l02p_2/m2 y7 dual 2 io_l05n_2 y9 i/o ta bl e 6 8 : spartan-3a dsp fg676 pinout for xc3sd3400a fpga (cont?d) bank xc3sd3400a pin name fg676 ball type 2 io_l12p_2 y10 i/o 2 io_l17p_2/rdwr_b y12 dual 2 io_l25n_2/gclk13 y13 gclk 2 io_l27p_2/gclk0 y14 gclk 2 io_l34n_2/d3 y15 dual 2 ip_2/vref_2 y16 vref 2 io_l43n_2 y17 i/o 2 io_l05p_2 w9 i/o 2 io_l09n_2 w10 i/o 2 io_l16n_2 w12 i/o 2 io_l20n_2 w13 i/o 2 io_l31n_2 w15 i/o 2 io_l46p_2 w17 i/o 2 io_l09p_2 v10 i/o 2 io_l13p_2 v11 i/o 2 io_l16p_2 v12 i/o 2 io_l20p_2 v13 i/o 2 io_l31p_2 v14 i/o 2 io_l35p_2 v15 i/o 2 io_l42p_2 v16 i/o 2 io_l46n_2 v17 i/o 2 io_l13n_2 u11 i/o 2 io_l35n_2 u15 i/o 2 io_l42n_2 u16 i/o 2 io_l06n_2 af3 i/o 2 io_l07n_2 af4 i/o 2 io_l10p_2 af5 i/o 2 io_l18n_2 af8 i/o 2 io_l19n_2/vs0 af9 dual 2 io_l22n_2/d6 af10 dual 2 io_l24p_2/d5 af12 dual 2 io_l26p_2/gclk14 af13 gclk 2 io_l28p_2/gclk2 af14 gclk 2 ip_2/vref_2 af15 vref 2 ip_2/vref_2 af17 vref 2 io_l36p_2/d2 af18 dual 2 io_l37p_2 af19 i/o 2 io_l39p_2 af20 i/o 2 ip_2/vref_2 af22 vref ta b l e 6 8 : spartan-3a dsp fg676 pinout for xc3sd3400a fpga (cont?d) bank xc3sd3400a pin name fg676 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 91 2 io_l48p_2 af23 i/o 2 io_l52p_2/d0/din/miso af24 dual 2 io_l51p_2 af25 i/o 2 io_l06p_2 ae3 i/o 2 io_l07p_2 ae4 i/o 2 io_l10n_2 ae6 i/o 2 io_l11n_2 ae7 i/o 2 io_l18p_2 ae8 i/o 2 io_l19p_2/vs1 ae9 dual 2 io_l22p_2/d7 ae10 dual 2 io_l24n_2/d4 ae12 dual 2 io_l26n_2/gclk15 ae13 gclk 2 io_l28n_2/gclk3 ae14 gclk 2 io_l32n_2/dout ae15 dual 2 io_l33p_2 ae17 i/o 2 io_l36n_2/d1 ae18 dual 2 io_l37n_2 ae19 i/o 2 io_l39n_2 ae20 i/o 2 io_l44p_2 ae21 i/o 2 io_l48n_2 ae23 i/o 2 io_l52n_2/cclk ae24 dual 2 io_l51n_2 ae25 i/o 2 io_l01n_2/m0 ad4 dual 2 io_l08n_2 ad6 i/o 2 io_l11p_2 ad7 i/o 2 ip_2 ad9 input 2 ip_2 ad10 input 2 io_l23p_2 ad11 i/o 2 ip_2/vref_2 ad12 vref 2 io_l29p_2 ad14 i/o 2 io_l32p_2/awake ad15 pwrmgmt 2 ip_2 ad16 input 2 io_l33n_2 ad17 i/o 2 io_l40p_2 ad19 i/o 2 io_l41p_2 ad20 i/o 2 io_l44n_2 ad21 i/o 2 io_l45p_2 ad22 i/o 2 io_l01p_2/m1 ac4 dual 2 io_l08p_2 ac6 i/o ta bl e 6 8 : spartan-3a dsp fg676 pinout for xc3sd3400a fpga (cont?d) bank xc3sd3400a pin name fg676 ball type 2 io_l14p_2 ac8 i/o 2 io_l15n_2 ac9 i/o 2 ip_2/vref_2 ac10 vref 2 io_l23n_2 ac11 i/o 2 io_l21n_2 ac12 i/o 2 ip_2 ac13 input 2 io_l29n_2 ac14 i/o 2 io_l30p_2 ac15 i/o 2 io_l38p_2 ac16 i/o 2 ip_2 ac17 input 2 io_l40n_2 ac19 i/o 2 io_l41n_2 ac20 i/o 2 io_l45n_2 ac21 i/o 2 io_2 ac22 i/o 2 ip_2/vref_2 ab6 vref 2 io_l14n_2 ab7 i/o 2 io_l15p_2 ab9 i/o 2 io_l21p_2 ab12 i/o 2 ip_2 ab13 input 2 io_l30n_2/mosi/csi_b ab15 dual 2 io_l38n_2 ab16 i/o 2 io_l47p_2 ab18 i/o 2 io_l02n_2/cso_b aa7 dual 2 ip_2/vref_2 aa9 vref 2 io_l12n_2 aa10 i/o 2 io_l17n_2/vs2 aa12 dual 2 io_l25p_2/gclk12 aa13 gclk 2 io_l27n_2/gclk1 aa14 gclk 2 io_l34p_2/init_b aa15 dual 2 io_l43p_2 aa17 i/o 2 io_l47n_2 aa18 i/o 2 ip_2/vref_2 aa20 vref 2 vcco_2 w11 vcco 2 vcco_2 w16 vcco 2 vcco_2 af7 vcco 2 vcco_2 ae5 vcco 2 vcco_2 ae11 vcco 2 vcco_2 ae16 vcco 2 vcco_2 ae22 vcco ta b l e 6 8 : spartan-3a dsp fg676 pinout for xc3sd3400a fpga (cont?d) bank xc3sd3400a pin name fg676 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 92 2 vcco_2 ab8 vcco 2 vcco_2 ab14 vcco 2 vcco_2 ab19 vcco 3 io_l53p_3 y1 i/o 3 io_l53n_3 y2 i/o 3 ip_3 y3 input 3 io_l57p_3 y5 i/o 3 io_l57n_3 y6 i/o 3 ip_l50p_3 w1 input 3 ip_l50n_3/vref_3 w2 vref 3 io_l52p_3 w3 i/o 3 io_l52n_3 w4 i/o 3 io_l63n_3 w6 i/o 3 io_l63p_3 w7 i/o 3 io_l47p_3 v1 i/o 3 io_l47n_3 v2 i/o 3 ip_l46n_3 v4 input 3 io_l49n_3 v5 i/o 3 io_l59n_3 v6 i/o 3 io_l59p_3 v7 i/o 3 io_l61n_3 v8 i/o 3 io_l44p_3 u1 i/o 3 io_l44n_3 u2 i/o 3 ip_l46p_3 u3 input 3 io_l42n_3 u4 i/o 3 io_l49p_3 u5 i/o 3 io_l51n_3 u6 i/o 3 io_l56p_3 u7 i/o 3 io_l56n_3 u8 i/o 3 io_l61p_3 u9 i/o 3 io_l38p_3 t3 i/o 3 io_l38n_3 t4 i/o 3 io_l42p_3 t5 i/o 3 io_l51p_3 t7 i/o 3 io_l48n_3 t9 i/o 3 io_l48p_3 t10 i/o 3 io_l36p_3/vref_3 r1 vref 3 io_l36n_3 r2 i/o 3 io_l37p_3 r3 i/o ta bl e 6 8 : spartan-3a dsp fg676 pinout for xc3sd3400a fpga (cont?d) bank xc3sd3400a pin name fg676 ball type 3 io_l37n_3 r4 i/o 3 io_l40p_3 r5 i/o 3 io_l40n_3 r6 i/o 3 io_l45n_3 r7 i/o 3 io_l45p_3 r8 i/o 3 io_l43n_3 r9 i/o 3 io_l43p_3/vref_3 r10 vref 3 io_l33p_3/lhclk2 p1 lhclk 3 io_l33n_3/irdy2/lhclk3 p2 lhclk 3 io_l34n_3/lhclk5 p3 lhclk 3 io_l34p_3/lhclk4 p4 lhclk 3 io_l39n_3 p6 i/o 3 io_l39p_3 p7 i/o 3 io_l41p_3 p8 i/o 3 io_l41n_3 p9 i/o 3 io_l35n_3/lhclk7 p10 lhclk 3 io_l31p_3 n1 i/o 3 io_l31n_3 n2 i/o 3 io_l30n_3 n4 i/o 3 io_l30p_3 n5 i/o 3 io_l32p_3/lhclk0 n6 lhclk 3 io_l32n_3/lhclk1 n7 lhclk 3 io_l35p_3/trdy2/lhclk6 n9 lhclk 3 io_l29n_3/vref_3 m1 vref 3 io_l29p_3 m2 i/o 3 io_l27n_3 m3 i/o 3 io_l27p_3 m4 i/o 3 io_l28p_3 m5 i/o 3 io_l28n_3 m6 i/o 3 io_l26n_3 m7 i/o 3 io_l26p_3 m8 i/o 3 io_l21n_3 m9 i/o 3 io_l21p_3 m10 i/o 3 io_l25n_3 l3 i/o 3 io_l25p_3 l4 i/o 3 io_l18n_3 l7 i/o 3 io_l15n_3 l9 i/o 3 io_l15p_3 l10 i/o 3 ip_l24n_3 k1 input ta b l e 6 8 : spartan-3a dsp fg676 pinout for xc3sd3400a fpga (cont?d) bank xc3sd3400a pin name fg676 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 93 3 io_l23n_3 k2 i/o 3 io_l23p_3 k3 i/o 3 io_l22n_3 k4 i/o 3 io_l22p_3 k5 i/o 3 io_l18p_3 k6 i/o 3 io_l13p_3 k7 i/o 3 io_l05n_3 k8 i/o 3 io_l05p_3 k9 i/o 3 ip_l24p_3 j1 input 3 ip_l20n_3/vref_3 j2 vref 3 ip_l20p_3 j3 input 3 io_l19n_3 j4 i/o 3 io_l19p_3 j5 i/o 3 io_l13n_3 j6 i/o 3 io_l10p_3 j7 i/o 3 io_l01p_3 j8 i/o 3 io_l01n_3 j9 i/o 3 io_l17n_3 h1 i/o 3 io_l17p_3 h2 i/o 3 ip_3/vref_3 h4 vref 3 io_l10n_3 h6 i/o 3 io_l03n_3 h7 i/o 3 ip_3 g1 input 3 io_l14p_3 g3 i/o 3 io_l09n_3 g4 i/o 3 io_l03p_3 g6 i/o 3 io_l11n_3 f2 i/o 3 io_l14n_3 f3 i/o 3 io_l07n_3 f4 i/o 3 io_l09p_3 f5 i/o 3 io_l11p_3 e1 i/o 3 io_l07p_3 e3 i/o 3 io_l06n_3 e4 i/o 3 io_l06p_3 d3 i/o 3 ip_3/vref_3 c1 vref 3 io_l02n_3 b1 i/o 3 io_l02p_3 b2 i/o 3 ip_l66p_3 ae1 input 3 ip_l66n_3/vref_3 ae2 vref ta bl e 6 8 : spartan-3a dsp fg676 pinout for xc3sd3400a fpga (cont?d) bank xc3sd3400a pin name fg676 ball type 3 io_l65p_3 ad1 i/o 3 io_l65n_3 ad2 i/o 3 io_l60n_3 ac1 i/o 3 io_l64p_3 ac2 i/o 3 io_l64n_3 ac3 i/o 3 io_l60p_3 ab1 i/o 3 io_l55p_3 aa2 i/o 3 io_l55n_3 aa3 i/o 3 ip_3/vref_3 aa5 vref 3 vcco_3 w5 vcco 3 vcco_3 t2 vcco 3 vcco_3 t8 vcco 3 vcco_3 p5 vcco 3 vcco_3 l2 vcco 3 vcco_3 l8 vcco 3 vcco_3 h5 vcco 3 vcco_3 e2 vcco 3 vcco_3 c2 vcco 3 vcco_3 ab2 vcco gnd gnd w8 gnd gnd gnd w14 gnd gnd gnd w19 gnd gnd gnd w24 gnd gnd gnd w25 gnd gnd gnd v3 gnd gnd gnd u10 gnd gnd gnd u13 gnd gnd gnd u17 gnd gnd gnd u25 gnd gnd gnd t1 gnd gnd gnd t6 gnd gnd gnd t12 gnd gnd gnd t14 gnd gnd gnd t16 gnd gnd gnd t21 gnd gnd gnd t26 gnd gnd gnd r11 gnd gnd gnd r13 gnd gnd gnd r15 gnd ta b l e 6 8 : spartan-3a dsp fg676 pinout for xc3sd3400a fpga (cont?d) bank xc3sd3400a pin name fg676 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 94 gnd gnd p12 gnd gnd gnd p16 gnd gnd gnd p19 gnd gnd gnd p24 gnd gnd gnd n3 gnd gnd gnd n8 gnd gnd gnd n11 gnd gnd gnd n15 gnd gnd gnd m12 gnd gnd gnd m14 gnd gnd gnd m16 gnd gnd gnd l1 gnd gnd gnd l6 gnd gnd gnd l11 gnd gnd gnd l13 gnd gnd gnd l15 gnd gnd gnd l21 gnd gnd gnd l26 gnd gnd gnd k10 gnd gnd gnd k17 gnd gnd gnd j24 gnd gnd gnd h3 gnd gnd gnd h8 gnd gnd gnd h14 gnd gnd gnd h19 gnd gnd gnd g2 gnd gnd gnd g5 gnd gnd gnd g16 gnd gnd gnd f1 gnd gnd gnd f6 gnd gnd gnd f11 gnd gnd gnd f16 gnd gnd gnd f21 gnd gnd gnd f26 gnd gnd gnd e9 gnd gnd gnd d2 gnd gnd gnd d15 gnd gnd gnd d19 gnd gnd gnd c3 gnd ta bl e 6 8 : spartan-3a dsp fg676 pinout for xc3sd3400a fpga (cont?d) bank xc3sd3400a pin name fg676 ball type gnd gnd c9 gnd gnd gnd c14 gnd gnd gnd c19 gnd gnd gnd c24 gnd gnd gnd b24 gnd gnd gnd b25 gnd gnd gnd af1 gnd gnd gnd af6 gnd gnd gnd af11 gnd gnd gnd af16 gnd gnd gnd af21 gnd gnd gnd af26 gnd gnd gnd ad3 gnd gnd gnd ad5 gnd gnd gnd ad8 gnd gnd gnd ad13 gnd gnd gnd ad18 gnd gnd gnd ad23 gnd gnd gnd ad24 gnd gnd gnd ac5 gnd gnd gnd ac7 gnd gnd gnd ac18 gnd gnd gnd ab3 gnd gnd gnd ab10 gnd gnd gnd ab20 gnd gnd gnd aa1 gnd gnd gnd aa4 gnd gnd gnd aa6 gnd gnd gnd aa11 gnd gnd gnd aa16 gnd gnd gnd aa19 gnd gnd gnd aa21 gnd gnd gnd aa26 gnd gnd gnd a1 gnd gnd gnd a5 gnd gnd gnd a6 gnd gnd gnd a11 gnd gnd gnd a16 gnd gnd gnd a21 gnd ta b l e 6 8 : spartan-3a dsp fg676 pinout for xc3sd3400a fpga (cont?d) bank xc3sd3400a pin name fg676 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 95 gnd gnd a23 gnd gnd gnd a26 gnd vccaux suspend v20 pwrmgmt vccaux done ab21 config vccaux prog_b a2 config vccaux tdi g7 jtag vccaux tdo e23 jtag vccaux tms d4 jtag vccaux tck a25 jtag vccaux vccaux w26 vccaux vccaux vccaux v9 vccaux vccaux vccaux u14 vccaux vccaux vccaux t22 vccaux vccaux vccaux p17 vccaux vccaux vccaux n10 vccaux vccaux vccaux l5 vccaux vccaux vccaux k13 vccaux vccaux vccaux j18 vccaux vccaux vccaux h23 vccaux vccaux vccaux g26 vccaux vccaux vccaux f9 vccaux vccaux vccaux e5 vccaux vccaux vccaux e16 vccaux vccaux vccaux e20 vccaux vccaux vccaux e22 vccaux vccaux vccaux d1 vccaux vccaux vccaux af2 vccaux vccaux vccaux ab4 vccaux vccaux vccaux ab5 vccaux vccaux vccaux ab11 vccaux vccaux vccaux ab17 vccaux vccaux vccaux ab22 vccaux vccaux vccaux a24 vccaux vccint vccint y4 vccint vccint vccint y8 vccint vccint vccint y11 vccint vccint vccint y18 vccint vccint vccint y19 vccint vccint vccint w18 vccint ta bl e 6 8 : spartan-3a dsp fg676 pinout for xc3sd3400a fpga (cont?d) bank xc3sd3400a pin name fg676 ball type vccint vccint u12 vccint vccint vccint t11 vccint vccint vccint t13 vccint vccint vccint t15 vccint vccint vccint r12 vccint vccint vccint r14 vccint vccint vccint r16 vccint vccint vccint p11 vccint vccint vccint p13 vccint vccint vccint p14 vccint vccint vccint p15 vccint vccint vccint n12 vccint vccint vccint n13 vccint vccint vccint n14 vccint vccint vccint n16 vccint vccint vccint m11 vccint vccint vccint m13 vccint vccint vccint m15 vccint vccint vccint m17 vccint vccint vccint l12 vccint vccint vccint l14 vccint vccint vccint l16 vccint vccint vccint k15 vccint vccint vccint g18 vccint vccint vccint f10 vccint vccint vccint f18 vccint vccint vccint e6 vccint vccint vccint d5 vccint vccint vccint c4 vccint vccint vccint aa8 vccint ta b l e 6 8 : spartan-3a dsp fg676 pinout for xc3sd3400a fpga (cont?d) bank xc3sd3400a pin name fg676 ball type
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 96 user i/os by bank table 69 indicates how the available user-i/o pins are distributed between the four i/o banks on the fg676 package. the awake pin is counted as a dual-purpose i/o. ta bl e 6 9 : user i/os per bank for the xc3sd3400a in the fg676 package package edge i/o bank maximum i/os and input-only all possible i/o pins by type i/o input dual vref (1) clk to p 0 111 82 11 1 9 8 right 1 123 67 8 30 10 8 bottom 2 112 68 6 21 9 8 left 3 123 97 9 0 9 8 total 469 314 34 52 37 32 notes: 1. 26 vref are on input pins.
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 97 fg676 footprint ? xc3sd3400a fpga left half of package (top view) 314 i/o: unrestricted, general-purpose user i/o. 34 input: unrestricted, general-purpose input pin. 51 dual: configuration pins, then possible user i/o. 37 vref: user i/o or input voltage reference for bank. 32 clk: user i/o, input, or clock buffer input. 2 config: dedicated configuration pins. 2 suspend: dedicated suspend and dual-purpose awake power management pins 4 jtag: dedicated jtag port pins. 100 gnd: ground 40 vcco: output voltage supply for bank. 36 vccint: internal core supply voltage (+1.2v). 24 vccaux: auxiliary supply voltage. note: the boxes with question marks inside indicate pin differences from the xc3sd1800a device. please see the footprint migration differences section for more information. figure 17: fg676 package footprint for xc3sd3400a fpga (top view?left half) 12345678910111213 a gnd prog_ b i/o l51p_0 i/o l45p_0 gnd ? gnd vcco_0 ? i/o l38p_0 i/o l36p_0 i/o l33p_0 gnd i/o l29p_0 input b i/o l02n_3 i/o l02p_3 i/o l51n_0 i/o l45n_0 vcco_0 i/o l41p_0 i/o l42p_0 i/o l38n_0 i/o l36n_0 i/o l33n_0 vcco_0 i/o l29n_0 i/o l28p_0 gclk10 c input vref_3 ? vcco_3 ? gnd vccint ? i/o l44p_0 i/o l41n_0 i/o l42n_0 i/o l40p_0 gnd i/o l34p_0 i/o l32p_0 i/o l30n_0 i/o l28n_0 gclk11 d vccaux ? gnd ? i/o l06p_3 tms vccint ? i/o l44n_0 input vref_0 i/o l40n_0 i/o l37n_0 i/o l34n_0 i/o l32n_0 vref_0 input i/o l30p_0 e i/o l11p_3 vcco_3 i/o l07p_3 i/o l06n_3 vccaux vccint ? i/o l48n_0 vcco_0 gnd ? i/o l37p_0 input i/o l31p_0 vcco_0 f gnd i/o l11n_3 i/o l14n_3 i/o l07n_3 i/o l09p_3 gnd i/o l48p_0 i/o l52p_0 vref_0 vccaux ? vccint ? gnd i/o l31n_0 i/o l27p_0 gclk8 g input ? gnd ? i/o l14p_3 i/o l09n_3 gnd ? i/o l03p_3 tdi i/o l52n_0 pudc_b i/o l47p_0 i/o l46p_0 input vref_0 i/o l35p_0 i/o l27n_0 gclk9 h i/o l17n_3 i/o l17p_3 gnd input vref_3 ? vcco_3 i/o l10n_3 i/o l03n_3 gnd i/o l47n_0 i/o l46n_0 vcco_0 i/o l35n_0 input j input l24p_3 input l20n_3 vref_3 input l20p_3 i/o l19n_3 i/o l19p_3 i/o l13n_3 i/o l10p_3 i/o l01p_3 i/o l01n_3 input i/o l43p_0 i/o l39p_0 input k input l24n_3 i/o l23n_3 i/o l23p_3 i/o l22n_3 i/o l22p_3 i/o l18p_3 i/o l13p_3 i/o l05n_3 i/o l05p_3 gnd i/o l43n_0 i/o l39n_0 vccaux l gnd vcco_3 i/o l25n_3 i/o l25p_3 vccaux gnd i/o l18n_3 vcco_3 i/o l15n_3 i/o l15p_3 gnd vccint gnd m i/o l29n_3 vref_3 i/o l29p_3 i/o l27n_3 i/o l27p_3 i/o l28p_3 i/o l28n_3 i/o l26n_3 i/o l26p_3 i/o l21n_3 i/o l21p_3 vccint gnd vccint n i/o l31p_3 i/o l31n_3 gnd i/o l30n_3 i/o l30p_3 i/o l32p_3 lhclk0 i/o l32n_3 lhclk1 gnd i/o l35p_3 trdy2 lhclk6 vccaux gnd vccint vccint p i/o l33p_3 lhclk2 i/o l33n_3 irdy2 lhclk3 i/o l34n_3 lhclk5 i/o l34p_3 lhclk4 vcco_3 i/o l39n_3 i/o l39p_3 i/o l41p_3 i/o l41n_3 i/o l35n_3 lhclk7 vccint gnd vccint r i/o l36p_3 vref_3 i/o l36n_3 i/o l37p_3 i/o l37n_3 i/o l40p_3 i/o l40n_3 i/o l45n_3 i/o l45p_3 i/o l43n_3 i/o l43p_3 vref_3 gnd vccint gnd t gnd vcco_3 i/o l38p_3 i/o l38n_3 i/o l42p_3 gnd i/o l51p_3 vcco_3 i/o l48n_3 i/o l48p_3 vccint gnd vccint u i/o l44p_3 i/o l44n_3 input l46p_3 i/o l42n_3 i/o l49p_3 i/o l51n_3 i/o l56p_3 i/o l56n_3 i/o l61p_3 gnd i/o l13n_2 vccint gnd bank 0 bank 3 v i/o l47p_3 i/o l47n_3 gnd input l46n_3 i/o l49n_3 i/o l59n_3 i/o l59p_3 i/o l61n_3 vccaux i/o l09p_2 i/o l13p_2 i/o l16p_2 i/o l20p_2 w input l50p_3 input l50n_3 vref_3 i/o l52p_3 i/o l52n_3 vcco_3 i/o l63n_3 i/o l63p_3 gnd i/o l05p_2 i/o l09n_2 vcco_2 i/o l16n_2 i/o l20n_2 y i/o l53p_3 i/o l53n_3 input ? vccint ? i/o l57p_3 i/o l57n_3 i/o l02p_2 m2 vccint ? i/o l05n_2 i/o l12p_2 vccint ? i/o l17p_2 rdwr_b i/o l25n_2 gclk13 a a gnd i/o l55p_3 i/o l55n_3 gnd ? input vref_3 ? gnd i/o l02n_2 cso_b vccint ? input vref_2 i/o l12n_2 gnd i/o l17n_2 vs2 i/o l25p_2 gclk12 a b i/o l60p_3 vcco_3 gnd ? vccaux ? vccaux input vref_2 i/o l14n_2 vcco_2 i/o l15p_2 gnd ? vccaux i/o l21p_2 input a c i/o l60n_3 i/o l64p_3 i/o l64n_3 i/o l01p_2 m1 gnd ? i/o l08p_2 gnd ? i/o l14p_2 i/o l15n_2 input vref_2 i/o l23n_2 i/o l21n_2 input a d i/o l65p_3 i/o l65n_3 gnd i/o l01n_2 m0 gnd ? i/o l08n_2 i/o l11p_2 gnd input input i/o l23p_2 input vref_2 gnd a e input l66p_3 input l66n_3 vref_3 i/o l06p_2 i/o l07p_2 vcco_2 i/o l10n_2 i/o l11n_2 i/o l18p_2 i/o l19p_2 vs1 i/o l22p_2 d7 vcco_2 i/o l24n_2 d4 i/o l26n_2 gclk15 a f gnd vccaux ? i/o l06n_2 i/o l07n_2 i/o l10p_2 gnd vcco_2 ? i/o l18n_2 i/o l19n_2 vs0 i/o l22n_2 d6 gnd i/o l24p_2 d5 i/o l26p_2 gclk14 bank 2
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 98 right half of fg676 package (top view) figure 17: fg676 package footprint for xc3sd3400a fpga (top view?right half) 14 15 16 17 18 19 20 21 22 23 24 25 26 i/o l26n_0 gclk7 i/o l23n_0 gnd input i/o l18n_0 i/o l15n_0 i/o l14n_0 gnd i/o l07n_0 gnd ? vccaux ? tck gnd a i/o l26p_0 gclk6 i/o l23p_0 vcco_0 i/o l19n_0 i/o l18p_0 i/o l15p_0 i/o l14p_0 vref_0 i/o l09n_0 vcco_0 i/o l07p_0 gnd ? ? input vref_1 ? b gnd i/o l22n_0 i/o l21n_0 i/o l19p_0 i/o l17n_0 gnd i/o l11n_0 i/o l09p_0 i/o l05n_0 i/o l06n_0 gnd i/o l63n_1 a23 i/o l63p_1 a22 c input vref_0 gnd ? i/o l22p_0 i/o l21p_0 i/o l17p_0 gnd ? i/o l11p_0 i/o l10n_0 i/o l05p_0 i/o l06p_0 i/o l61n_1 i/o l61p_1 i/o l60n_1 d i/o l24p_0 i/o l20n_0 vref_0 vccaux i/o l13n_0 input vcco_0 vccaux ? i/o l10p_0 vccaux tdo i/o l56p_1 vcco_1 i/o l60p_1 e i/o l24n_0 i/o l20p_0 gnd i/o l13p_0 vccint ? i/o l02n_0 i/o l01n_0 gnd i/o l58p_1 vref_1 i/o l56n_1 i/o l54n_1 i/o l54p_1 gnd f input i/o l16p_0 gnd ? i/o l08n_0 vccint ? i/o l02p_0 vref_0 i/o l01p_0 i/o l64n_1 a25 i/o l58n_1 i/o l51p_1 i/o l51n_1 input vref_1 ? vccaux ? g gnd i/o l16n_0 vcco_0 i/o l08p_0 input gnd i/o l64p_1 a24 i/o l62n_1 a21 vcco_1 vccaux ? input ? ? input vref_1 ? h i/o l25n_0 gclk5 input i/o l12p_0 input vref_0 vccaux i/o l59p_1 i/o l59n_1 i/o l62p_1 a20 i/o l49n_1 i/o l49p_1 gnd i/o l43n_1 a19 i/o l43p_1 a18 j i/o l25p_0 gclk4 vccint i/o l12n_0 gnd i/o l57n_1 i/o l57p_1 i/o l53n_1 i/o l50n_1 i/o l46n_1 i/o l46p_1 input l40p_1 i/o l41p_1 i/o l41n_1 k vccint gnd vccint i/o l55n_1 i/o l55p_1 vcco_1 i/o l53p_1 gnd i/o l50p_1 input l40n_1 i/o l38p_1 a12 vcco_1 gnd l gnd vccint gnd vccint i/o l47n_1 i/o l47p_1 i/o l42n_1 a17 i/o l45p_1 i/o l45n_1 i/o l38n_1 a13 input l36p_1 vref_1 i/o l35n_1 a11 i/o l35p_1 a10 m vccint gnd vccint i/o l39n_1 a15 i/o l39p_1 a14 i/o l34n_1 rhclk7 i/o l42p_1 a16 i/o l37n_1 vcco_1 input l36n_1 i/o l33n_1 rhclk5 input l32n_1 input l32p_1 n vccint vccint gnd vccaux i/o l34p_1 irdy1 rhclk6 gnd i/o l30n_1 rhclk1 i/o l30p_1 rhclk0 i/o l37p_1 i/o l33p_1 rhclk4 gnd i/o l31n_1 trdy1 rhclk3 i/o l31p_1 rhclk2 p vccint gnd vccint i/o l27n_1 a7 i/o l27p_1 a6 i/o l22p_1 i/o l22n_1 i/o l25p_1 a2 i/o l25n_1 a3 input l28p_1 vref_1 input l28n_1 i/o l29p_1 a8 i/o l29n_1 a9 r gnd vccint gnd i/o l17n_1 i/o l17p_1 vcco_1 i/o l14n_1 gnd vccaux i/o l26p_1 a4 i/o l26n_1 a5 vcco_1 gnd t vccaux i/o l35n_2 i/o l42n_2 gnd i/o l12n_1 i/o l12p_1 i/o l10n_1 i/o l14p_1 i/o l21n_1 i/o l23p_1 i/o l23n_1 vref_1 gnd ? input vref_1 ? u bank 0 bank 1 i/o l31p_2 i/o l35p_2 i/o l42p_2 i/o l46n_2 i/o l08p_1 i/o l08n_1 suspen d i/o l10p_1 i/o l18n_1 i/o l21p_1 i/o l19p_1 i/o l19n_1 input vref_1 ? v gnd i/o l31n_2 vcco_2 i/o l46p_2 vccint ? gnd i/o l04p_1 i/o l04n_1 vcco_1 i/o l18p_1 gnd gnd ? vccaux ? w i/o l27p_2 gclk0 i/o l34n_2 d3 input vref_2 i/o l43n_2 vccint ? ? i/o l01p_1 hdc i/o l01n_1 ldc2 i/o l13p_1 i/o l13n_1 i/o l15p_1 i/o l15n_1 input ? y i/o l27n_2 gclk1 i/o l34p_2 init_b gnd i/o l43p_2 i/o l47n_2 gnd ? input vref_2 gnd i/o l09p_1 i/o l09n_1 i/o l11p_1 i/o l11n_1 gnd a a vcco_2 i/o l30n_2 mosi csi _ b i/o l38n_2 vccaux ? i/o l47p_2 vcco_2 gnd ? done vccaux i/o l07p_1 i/o l07n_1 vref_1 vcco_1 i/o l06n_1 a b i/o l29n_2 i/o l30p_2 i/o l38p_2 input gnd ? i/o l40n_2 i/o l41n_2 i/o l45n_2 i/o 2 i/o l03p_1 a0 i/o l03n_1 a1 i/o l05n_1 i/o l06p_1 a c i/o l29p_2 i/o l32p_2 awake input i/o l33n_2 gnd i/o l40p_2 i/o l41p_2 i/o l44n_2 i/o l45p_2 gnd ? gnd i/o l02n_1 ldc0 i/o l05p_1 a d i/o l28n_2 gclk3 i/o l32n_2 dout vcco_2 i/o l33p_2 i/o l36n_2 d1 i/o l37n_2 i/o l39n_2 i/o l44p_2 vcco_2 i/o l48n_2 i/o l52n_2 cclk i/o l51n_2 i/o l02p_1 ldc1 a e i/o l28p_2 gclk2 input vref_2 gnd input vref_2 i/o l36p_2 d2 i/o l37p_2 i/o l39p_2 gnd input vref_2 i/o l48p_2 i/o l52p_2 d0 din/miso i/o l51p_2 gnd a f bank 2
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 99 footprint migration differences there are multiple migration footprint differences between the xc3sd1800a and the xc3sd3400a in the fg676 package. these migration footprint differences are shown in ta b l e 7 0 . migration from the xc3s1400a spartan-3a device in the fg676 package to a spartan-3a dsp device in the fg676 package is also possible. the xc3s1800a pin migration differences have been added to ta bl e 7 0 for designs migrating between these devices. ta bl e 7 0 : fg676 footprint migration differences fg676 ball spartan-3a spartan-3a dsp spartan-3a dsp fg676 ball xc3s1400a type xc3s1400a bank xc3sd1800a type xc3sd1800a bank xc3sd3400a type xc3sd3400a bank g16 ip_0 0 ip_0 0 gnd gnd g16 g18 n.c. n.c. ip_0 0 vccint vccint g18 f9 n.c. n.c. ip_0 0 vccaux vccaux f9 f10 ip_0 0 ip_0 0 vccint vccint f10 f18 n.c. n.c. ip_0 0 vccint vccint f18 e6 n.c. n.c. ip_0 0 vccint vccint e6 e9 n.c. n.c. ip_0 0 gnd gnd e9 e20 ip_0 0 ip_0 0 vccaux vccaux e20 d5 n.c. n.c. ip_0 0 vccint vccint d5 d15 ip_0 0 ip_0 0 gnd gnd d15 d19 ip_0 0 ip_0 0 gnd gnd d19 c4 ip_0 0 ip_0 0 vccint vccint c4 b24 n.c. n.c. ip_0 0 gnd gnd b24 a5 ip_0 0 ip_0 0 gnd gnd a5 a7 ip_0 0 ip_0 0 vcco_0 0 a7 a23 ip_0 0 ip_0 0 gnd gnd a23 a24 n.c. n.c. ip_0 0 vccaux vccaux a24 y26 ip_l16n_1 1 ip_l16n_1 1 ip_1 1 y26 w25 ip_l16p_1 1 ip_l16p_1 1 gnd gnd w25 w26 ip_l20p_1 1 ip_l20p_1 1 vccaux vccaux w26 v26 ip_l20n_1/ vref_1 1 ip_l20n_1/ vref_1 1 ip_1/vref_1 1 v26 u25 ip_l24p_1 1 ip_l24p_1 1 gnd gnd u25 u26 ip_l24n_1/ vref_1 1 ip_l24n_1/ vref_1 1 ip_1/vref_1 1 u26 h23 ip_l48p_1 1 ip_l48p_1 1 vccaux vccaux h23 h24 ip_l48n_1 1 ip_l48n_1 1 ip_1 1 h24 h25 ip_l44n_1 1 ip_l44n_1 1 vcco_1 1 h25 h26 ip_l44p_1/ vref_1 1 ip_l44p_1/ vref_1 1 ip_1/vref_1 1 h26 g25 ip_l52n_1/ vref_1 1 ip_l52n_1/ vref_1 1 ip_1/vref_1 1 g25 g26 ip_l52p_1 1 ip_l52p_1 1 vccaux vccaux g26 b25 ip_l65n_1 1 ip_l65 n_1 1 gnd gnd b25 b26 ip_l65p_1/ vref_1 1 ip_l65p_1/ vref_1 1 ip_1/vref_1 1 b26
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 100 migration recommendations there are multiple pinout differences between the xc3sd1800a and the xc3sd3400a fpgas in the fg676 package. please note the differences between the two devices from ta bl e 7 0 and take the necessary precautions. y8 n.c. n.c. ip_2 2 vccint vccint y8 y11 ip_2 2 ip_2 2 vccint vccint y11 y18 n.c. n.c. ip_2 2 vccint vccint y18 y19 n.c. n.c. ip_2/vref_2 2 vccint vccint y19 w18 n.c. n.c. ip_2 2 vccint vccint w18 af2 ip_2 2 ip_2 2 vccaux vccaux af2 af7 ip_2 2 ip_2 2 vcco_2 2 af7 ad5 n.c. n.c. ip_2 2 gnd gnd ad5 ad23 n.c. n.c. ip_2 2 gnd gnd ad23 ac5 n.c. n.c. ip_2 2 gnd gnd ac5 ac7 ip_2 2 ip_2 2 gnd gnd ac7 ac18 ip_2 2 ip_2 2 gnd gnd ac18 ab10 ip_2/vref_2 2 ip_2/vref_2 2 gnd gnd ab10 ab17 ip_2 2 ip_2 2 vccaux vccaux ab17 ab20 ip_2 2 ip_2 2 gnd gnd ab20 aa8 n.c. n.c. ip_2 2 vccint vccint aa8 aa19 ip_2 2 ip_2 2 gnd gnd aa19 ac22n.c.n.c.io_22io_22ac22 y3 ip_l54p_3 3 ip_l54p_3 3 ip_3 3 y3 y4 ip_l54n_3 3 ip_l54n_3 3 vccint vccint y4 h4 ip_l12n_3/ vref_3 3 ip_l12n_3/ vref_3 3 ip_3/vref_3 3 h4 g1 ip_l16n_3 3 ip_l16n_3 3 ip_3 3 g1 g2 ip_l16p_3 3 ip_l16p_3 3 gnd gnd g2 g5 ip_l12p_3 3 ip_l12p_3 3 gnd gnd g5 d1 ip_l08n_3 3 ip_l08n_3 3 vccaux vccaux d1 d2 ip_l08p_3 3 ip_l08p_3 3 gnd gnd d2 c1 ip_l04n_3/ vref_3 3 ip_l04n_3/ vref_3 3 ip_3/vref_3 3 c1 c2 ip_l04p_3 3 ip_l04p_3 3 vcco_3 3 c2 ab3 ip_l62p_3 3 ip_l62p_3 3 gnd gnd ab3 ab4 ip_l62n_3 3 ip_l62n_3 3 vccaux vccaux ab4 aa4 ip_l58p_3 3 ip_l58p_3 3 gnd gnd aa4 aa5 ip_l58n_3/ vref_3 3 ip_l58n_3/ vref_3 3 ip_3/vref_3 3 aa5 ta bl e 7 0 : fg676 footprint migration differences (cont?d) fg676 ball spartan-3a spartan-3a dsp spartan-3a dsp fg676 ball xc3s1400a type xc3s1400a bank xc3sd1800a type xc3sd1800a bank xc3sd3400a type xc3sd3400a bank
spartan-3a dsp fpga family: pinout descriptions ds610 (v3.0) october 4, 2010 www.xilinx.com product specification 101 revision history the following table shows the revision history for this document. date version revision 04/02/07 1.0 initial xilinx release. 05/25/07 1.1 updates to ta bl e 5 9 , ta bl e 6 3 , ta bl e 6 4 , ta b l e 6 5 , ta b l e 6 6 , ta b l e 6 7 , ta bl e 6 8 , ta bl e 6 9 . corrected vref pins in xc3s1800a fg676 ( ta bl e 7 0 ). updated fg676 package footprints for xc3sd1800a fpga ( figure 16 ) and xc3sd3400a fpga ( figure 17 ). minor edits. 06/18/07 1.2 updated for production release. 07/16/07 2.0 added low-power options. added advance thermal data to ta bl e 6 2 . 06/02/08 2.1 added package overview section. updated thermal characteristics in ta bl e 6 2 . corrected name for ab14 in cs484 in ta b l e 6 3 . updated links. 03/11/09 2.2 corrected bank designation for suspend to vccaux. 10/04/10 3.0 revision update to match other data sheet modules.

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